Patents by Inventor John K. DeBrosse
John K. DeBrosse has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140211550Abstract: Embodiments are directed to detecting a state of a memory element in a memory device, comprising: applying a pulse of a predetermined magnitude and duration to the memory element to induce a transition in the state of the memory element when a polarity of the pulse is opposite to the state, monitoring, by a device, a signal associated with the memory element to detect a presence or absence of a transition in the signal in an amount greater than a threshold, and determining the state of the memory element based on said monitoring.Type: ApplicationFiled: January 31, 2013Publication date: July 31, 2014Applicants: HEADWAY TECHNOLOGIES, INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jonathan Z. Sun, John K. DeBrosse, Po-Kang Wang
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Patent number: 8755213Abstract: A system and method for operating a bipolar memory cell array including a bidirectional access diode. The system includes a column voltage. The column voltage switch includes column voltages and an output electrically coupled to the bidirectional access diode. The column voltages include at least one write-one column voltage and at least one write-zero column voltage. The system also includes a row voltage switch. The row voltage switch includes row voltages and an output electrically coupled to the bidirectional access diode. The row voltages include at least one write-one row voltage and at least one write-zero row voltage. The system further includes a column decoder and a row decoder electrically coupled to a select line of the column voltage switch and row voltage switch, respectively. The system includes a write driver electrically coupled to the select lines of the row and column switches.Type: GrantFiled: February 29, 2012Date of Patent: June 17, 2014Assignee: International Business Machines CorporationInventors: John K. DeBrosse, Kailash Gopalakrishnan, Chung H. Lam, Jing Li
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Publication number: 20130223125Abstract: A system and method for operating a bipolar memory cell array including a bidirectional access diode. The system includes a column voltage. The column voltage switch includes column voltages and an output electrically coupled to the bidirectional access diode. The column voltages include at least one write-one column voltage and at least one write-zero column voltage. The system also includes a row voltage switch. The row voltage switch includes row voltages and an output electrically coupled to the bidirectional access diode. The row voltages include at least one write-one row voltage and at least one write-zero row voltage. The system further includes a column decoder and a row decoder electrically coupled to a select line of the column voltage switch and row voltage switch, respectively. The system includes a write driver electrically coupled to the select lines of the row and column switches.Type: ApplicationFiled: February 29, 2012Publication date: August 29, 2013Applicant: International Business Machines CorporationInventors: John K. DeBrosse, Kailash Gopalakrishnan, Chung H. Lam, Jing Li
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Patent number: 8456899Abstract: A method for operating a memory array device, includes initiating a write “0” state in the device, wherein the initiating the write “0” state includes inducing a first voltage in a word line of the device; and inducing a second voltage in a first bit line (BLTE) of the device.Type: GrantFiled: July 26, 2012Date of Patent: June 4, 2013Assignee: International Business Machines CorporationInventors: John K. DeBrosse, Yutaka Nakamura
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Patent number: 8456901Abstract: A system includes a processor and a memory array connected to the processor comprising a first memory cell comprising a first magnetic tunnel junction device having a first terminal connected to a first bit line and a second terminal, and a first field effect transistor having a source terminal connected to a second bit line, a gate terminal connected to a word line, and a drain terminal connected to the second terminal of the first magnetic tunnel junction device, and a second memory cell comprising a second magnetic tunnel junction device having a first terminal connected to a third bit line and a second terminal, and a second field effect transistor having a source terminal connected to the second bit line, a gate terminal connected to the word line, and a drain terminal connected to the second terminal of the second magnetic tunnel junction device.Type: GrantFiled: July 27, 2012Date of Patent: June 4, 2013Assignee: International Business Machines CorporationInventors: John K. DeBrosse, Yutaka Nakamura
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Patent number: 8446757Abstract: A memory array device comprising a first memory cell comprising a first magnetic tunnel junction device having a first terminal connected to a first bit line (BLTE) and a second terminal, and a first field effect transistor (FET) having a source terminal connected to a second bit line (BLC), a gate terminal connected to a word line (WL), and a drain terminal connected to the second terminal of the first magnetic tunnel junction device, and a second memory cell comprising, a second magnetic tunnel junction device having a first terminal connected to a third bit line (BLT0) and a second terminal, and a second field effect transistor (FET) having a source terminal connected to the second bit line (BLC), a gate terminal connected to the word line (WL), and a drain terminal connected to the second terminal of the second magnetic tunnel junction device.Type: GrantFiled: August 18, 2010Date of Patent: May 21, 2013Assignee: International Business Machines CorporationInventors: John K. DeBrosse, Yutaka Nakamura
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Patent number: 8370714Abstract: A method of reading and correcting data within a memory device that includes reading each data bit of a data word using a plurality of reference cells corresponding to each data bit, performing error detection on the read data bits, and correcting a read data bit when an error is detected using error correction code (ECC) and writing each corresponding reference cells to an original memory state thereof.Type: GrantFiled: January 8, 2010Date of Patent: February 5, 2013Assignee: International Business Machines CorporationInventors: John K. DeBrosse, Daniel C. Worledge
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Patent number: 8331125Abstract: A high density memory architecture comprising magnetic racetrack memory and a method of operation. The memory architecture comprises a plurality of magnetic memory structures, each the structure formed of magnetic material; a sensing device associated with each magnetic memory structure; first decoder device initiating a track select signal for activating a single magnetic memory structure from among the plurality to perform a bit read or bit storage operation; a bit drive device for applying a first signal to form a new magnetic memory domain associated with a bit value to be stored in the activated magnetic memory structure at a first position thereof during a bit storage operation; and, a second decoder applying a second signal for advancing each the formed magnetic memory domain toward a second position of the activated memory structure. The sensing device reads a memory bit value stored at a magnetic domain at the second position of the activated memory structure.Type: GrantFiled: August 26, 2009Date of Patent: December 11, 2012Assignee: International Business Machines CorporationInventor: John K. DeBrosse
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Publication number: 20120294071Abstract: A system includes a processor and a memory array connected to the processor comprising a first memory cell comprising a first magnetic tunnel junction device having a first terminal connected to a first bit line and a second terminal, and a first field effect transistor having a source terminal connected to a second bit line, a gate terminal connected to a word line, and a drain terminal connected to the second terminal of the first magnetic tunnel junction device, and a second memory cell comprising a second magnetic tunnel junction device having a first terminal connected to a third bit line and a second terminal, and a second field effect transistor having a source terminal connected to the second bit line, a gate terminal connected to the word line, and a drain terminal connected to the second terminal of the second magnetic tunnel junction device.Type: ApplicationFiled: July 27, 2012Publication date: November 22, 2012Applicant: International Business Machines CorporationInventors: John K. DeBrosse, Yutaka Nakamura
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Publication number: 20120287705Abstract: A method for operating a memory array device, includes initiating a write “0” state in the device, wherein the initiating the write “0” state includes inducing a first voltage in a word line of the device; and inducing a second voltage in a first bit line (BLTE) of the device.Type: ApplicationFiled: July 26, 2012Publication date: November 15, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John K. DeBrosse, Yutaka Nakamura
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Patent number: 8228706Abstract: In one embodiment, the invention is a magnetic shift register memory device. One embodiment of a memory cell includes a magnetic column including a plurality of magnetic domains, a reader coupled to the magnetic column, for reading data from the magnetic domains, a temporary memory for storing data read from the magnetic domains, and a writer coupled to the magnetic column, for writing data in the temporary memory to the magnetic domains.Type: GrantFiled: July 7, 2008Date of Patent: July 24, 2012Assignee: International Business Machines CorporationInventors: John K. DeBrosse, William J. Gallagher, Yu Lu
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Publication number: 20120182781Abstract: In one embodiment, the invention is a magnetic shift register memory device. One embodiment of a memory cell includes a magnetic column including a plurality of magnetic domains, a reader coupled to the magnetic column, for reading data from the magnetic domains, a temporary memory for storing data read from the magnetic domains, and a writer coupled to the magnetic column, for writing data in the temporary memory to the magnetic domains.Type: ApplicationFiled: March 27, 2012Publication date: July 19, 2012Applicant: International Business Machines CorporationInventors: JOHN K. DeBrosse, William J. Gallagher, Yu Lu
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Publication number: 20120044754Abstract: A memory array device comprising a first memory cell comprising a first magnetic tunnel junction device having a first terminal connected to a first bit line (BLTE) and a second terminal, and a first field effect transistor (FET) having a source terminal connected to a second bit line (BLC), a gate terminal connected to a word line (WL), and a drain terminal connected to the second terminal of the first magnetic tunnel junction device, and a second memory cell comprising, a second magnetic tunnel junction device having a first terminal connected to a third bit line (BLT0) and a second terminal, and a second field effect transistor (FET) having a source terminal connected to the second bit line (BLC), a gate terminal connected to the word line (WL), and a drain terminal connected to the second terminal of the second magnetic tunnel junction device.Type: ApplicationFiled: August 18, 2010Publication date: February 23, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John K. DeBrosse, Yutaka Nakamura
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Patent number: 8023305Abstract: A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures.Type: GrantFiled: June 10, 2008Date of Patent: September 20, 2011Assignee: International Business Machines CorporationInventors: Michael C. Gaidis, Lawrence A. Clevenger, Timothy J. Dalton, John K. DeBrosse, Louis L. C. Hsu, Carl Radens, Keith Kwong-Hon Wong, Chih-Chao Yang
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Patent number: 8009453Abstract: A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a write wire having a constriction therein, the constriction located at a point corresponding to the location of the plurality of discontinuities in the associated shift register structure.Type: GrantFiled: June 10, 2008Date of Patent: August 30, 2011Assignee: International Business Machines CorporationInventors: Michael C. Gaidis, Lawrence A. Clevenger, Timothy J. Dalton, John K. DeBrosse, Louis L. C. Hsu, Carl Radens, Keith Kwong-Hon Wong, Chih-Chao Yang
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Publication number: 20110173513Abstract: A method of reading and correcting data within a memory device that includes reading each data bit of a data word using a plurality of reference cells corresponding to each data bit, performing error detection on the read data bits, and correcting a read data bit when an error is detected using error correction code (ECC) and writing each corresponding reference cells to an original memory state thereof.Type: ApplicationFiled: January 8, 2010Publication date: July 14, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John K. DeBrosse, Daniel C. Worledge
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Publication number: 20110051490Abstract: A high density memory architecture comprising magnetic racetrack memory and a method of operation. The memory architecture comprises a plurality of magnetic memory structures, each the structure formed of magnetic material; a sensing device associated with each magnetic memory structure; first decoder device initiating a track select signal for activating a single magnetic memory structure from among the plurality to perform a bit read or bit storage operation; a bit drive device for applying a first signal to form a new magnetic memory domain associated with a bit value to be stored in the activated magnetic memory structure at a first position thereof during a bit storage operation; and, a second decoder applying a second signal for advancing each the formed magnetic memory domain toward a second position of the activated memory structure. The sensing device reads a memory bit value stored at a magnetic domain at the second position of the activated memory structure.Type: ApplicationFiled: August 26, 2009Publication date: March 3, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: John K. DeBrosse
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Publication number: 20100002486Abstract: In one embodiment, the invention is a magnetic shift register memory device. One embodiment of a memory cell includes a magnetic column including a plurality of magnetic domains, a reader coupled to the magnetic column, for reading data from the magnetic domains, a temporary memory for storing data read from the magnetic domains, and a writer coupled to the magnetic column, for writing data in the temporary memory to the magnetic domains.Type: ApplicationFiled: July 7, 2008Publication date: January 7, 2010Inventors: John K. DeBrosse, William J. Gallagher, Yu Lu
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Patent number: 7596045Abstract: A design structure embodied in a machine readable medium used in a design process includes an apparatus for initializing a reference cell in a toggle switched MRAM device, with a first sense amplifier configured for performing a first read operation of the reference cell by comparing current through the reference cell with the average current passing through a pair of data cells; a first latch for storing the result of the first read operation; a second latch for storing the result of a second read operation by the first sense amplifier, wherein the second read operation is performed following the first read operation and the inversion of the value of one of the pair of the data cells; a third latch for storing the result of a third read operation by the first sense amplifier, wherein the third read operation is performed following the second read operation and the inversion of the value of the other of the pair of the data cells; and a majority compare device configured to compare of the results of the firstType: GrantFiled: October 31, 2007Date of Patent: September 29, 2009Assignee: International Business Machines CorporationInventors: John K. DeBrosse, Mark C. H. Lamorey
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Patent number: 7535783Abstract: A precision sense amplifier apparatus includes a current source configured to introduce an adjustable reference current through a reference leg; a current mirror configured to mirror the reference current to a data leg, the data leg selectively coupled to a programmable resistance memory element; an active clamping device coupled to the data leg, and configured to clamp a fixed voltage across the memory element, thereby establishing a fixed current sinking capability thereof; and a differential sense amplifier having a first input thereof coupled to the data leg and a second input thereof coupled to the reference leg; wherein an output of the differential sense amplifier assumes a first logic state whenever the reference current is less than the fixed current sinking capability of the memory element, and assumes a second logic state whenever the reference current exceeds the fixed current sinking capability.Type: GrantFiled: October 1, 2007Date of Patent: May 19, 2009Assignee: International Business Machines CorporationInventors: John K. DeBrosse, Thomas M. Maffitt, Mark C. H. Lamorey