Abstract: A method and structure for a dynamic random access memory chip includes memory element arrays having bitlines, a sense amplifier shared by the arrays. The sense amplifier includes multiplexors connected to the bitlines, an equalizer circuit connected to the multiplexors and a timer circuit connecting first bitlines to the sense amplifier a time period after second bitlines are sensed by the sense amplifier, wherein the time period is less than the active phase of the row cycle.

Abstract: An isolation and gate planarization method for an integrated circuit chip and chips designed by the method. The method comprises generating a dummy gate conductor (GC) shape and biasing it to the underlying well. The method may further comprise generating an active area (AA) dummy shape underlying the GC dummy shape. Biasing may be to the same voltage as the underlying well, or may be to a different voltage to create a decoupling capacitor. The biasing may be accomplished by implanting a well contact on an active area shape, the contact being N+ over an N-well or P+ over a P-well.

Abstract: A method and apparatus for repairing a semiconductor memory device. A row redundancy replacement arrangement is provided to repair the memory device consisting of a first plurality of redundant true word lines and a second plurality of redundant complement word lines to simultaneously replace the same first number of first normal word lines and the same second number of the normal complement word lines. An address reordering scheme, preferably implemented as a word line selector circuit and controlled by redundancy control logic and address inputs, allows the redundant true (complement) word lines to replace the normal true (complement) word lines when making the repair. The redundancy replacement arrangement ensures that consistency of the bit map is maintained at all times, irrespective whether the memory device operates in a normal or in a redundancy mode. This approach introduces an added flexibility of incorporating the redundancy replacement without affecting the column access speed.

Abstract: A process sequence, cell structure, and cell layout for an eight square folded bit line dynamic random access memory (DRAM) cell allows a transfer device channel length of two lithographic features. The process sequence may allow elimination of deep trench collar or cap deposition, or reduction of word line to word line capacitance. The cell prepared by the method allows a two lithographic feature transfer device channel length in an eight square folded bit line DRAM cell. The method uses conventional processing techniques with no spacer defined features and uses conventional structures. The cell requires only one additional mask (GPC) and minimal additional processing. The process sequence starts with deep trench (DT) processing, followed by deposition of SiO.sub.2, planarization and pad strip. Then gate SiO.sub.2, polysilicon, and pad are deposited. The structure is etched using a shallow trench isolation mask and filled with SiO.sub.2.

Abstract: A process sequence, cell structure, and cell layout for an eight square folded bit line dynamic random access memory (DRAM) cell allows a transfer device channel length of two lithographic features. The process sequence may allow elimination of deep trench collar or cap deposition, or reduction of word line to word line capacitance. The cell prepared by the method allows a two lithographic feature transfer device channel length in an eight square folded bit line DRAM cell. The method uses conventional processing techniques with no spacer defined features and uses conventional structures. The cell requires only one additional mask (GPC) and minimal additional processing. The process sequence starts with deep trench (DT) processing, followed by deposition of SiO.sub.2, planarization and pad strip. Then gate SiO.sub.2, polysilicon, and pad are deposited. The structure is etched using a shallow trench isolation mask and filled with SiO.sub.2.

Abstract: In the Preferred embodiment of the present invention, a bit line pair is coupled through a pair of high-resistance pass gates to a sense amp. During sense, the high-resistance pass gates act in conjunction with the charge stored on the bit line pair as, effectively, a high-resistance passive load for the sense amp. A control circuit selectively switches on and off bit line equalization coincident with selectively passing either the equalization voltage or set voltages to the sense amp and an active sense amp load. Further, after it is set, the sense amp is selectively connected to LDLs through low-resistance column select pass gates. Therefore, the sense amp quickly discharges one of the connected LDL pair while the bit line voltage remains essentially unchanged. Thus, data is passed from the sense amp to a second sense amplifier and off chip. After data is passed to the LDLs, the control circuit enables the active sense amp load to pull the sense amp high side to a full up level.

Abstract: An SOI DRAM includes a direct body contact between the SOI layer and the silicon substrate, and field-shield isolation positioned on the surface of the SOI structure which extends over the direct body contact. Deep trench storage capacitors are positioned adjacent the direct body contact.

Abstract: An improved method for isolating electrical conductors which are positioned over each other is disclosed. These conductors would normally contact each other because of the somewhat imprecise patterning and etching steps used to fabricate a multitude of conductive elements, e.g., in a very dense semiconductor structure. The method involves forming a recess in the upper surface of the lower conductor, and then at least partially filling the recess with an oxide-type material. This method is particularly valuable in the construction of stacked capacitor cells. Cells prepared using this technique also form part of this invention.

Abstract: A Dynamic Random Access Memory (DRAM) including an array of memory cells arranged in rows and columns, a word line in each row responsive to a row address and, a pair of complementary bit lines in each column. The DRAM also includes a sense amp in each column connected between a sense enable and the pair of complementary bit lines. The sense amp is a pair of cross coupled NFETs, with the sources of the NFETs connected to the sense amp enable. A bit line pre-charge is connected to each pair of complementary bit lines. The bit line pre-charge is connected between the complementary bit line pair and a reference voltage. A test control circuit selectively holds the sense amp disabled and the bit line pairs in a pre-charge state in response to a test control signal. An active sense amp load connected between the sense amp and a load enable latches data in the sense amp. The active sense amp load is a pair of cross coupled PFETs connected to the sense amp with the sources of the PFETs connected to the load enable.

Abstract: An exchangeable hierarchical data line structure includes a first half of a unit circuit, a second half of a unit circuit and a common sense amplifier row disposed therebetween. The common sense amplifier row includes a common plurality of sense amplifiers and a common local data line. The structure includes a first set of master data lines with a first master data line and a third master data line, and a second set of master data lines with a second master data line and a fourth master data line. The master data lines form a master bus transversing the direction of the common local data line. The structure includes first switch circuitry to selectively couple signals between the common local data line and the first master data line. The structure includes second switch circuitry to selectively couple signals between the common local data line and the second master data line.

Abstract: An interconnection array layout and method are provided for a plurality of paired line conductors of a given length extending principally parallel. A single crossing region traverses the paired line conductors intermediate the given length, wherein the line conductors of each pair of line conductors cross such that inter-pair capacitive coupling is matched. Intra-pair capacitive coupling is avoided by separating the line conductors of each pair of line conductors by two pitches and disposing therebetween a line conductor of a different pair of line conductors. Applications include semiconductor memory arrays, such as DRAM structures, and address/data busses wherein paired true/complement line conductors are employed.

Abstract: An SOI deep-trench DRAM having body contacts and field shield isolation makes contact between the SOI device layer and a buried conductive layer below the insulating layer at selected sites between adjacent deep trench capacitors. The buried layer may be biased to provide better attraction for holes.

Abstract: An SOI deep-trench DRAM having body contacts and field shield isolation makes contact between the SOI device layer and the field shield layer at selected sites between adjacent deep trench capacitors. The field shield layer is biased negative to provide better isolation and to set the body potential of the array transistors.

Abstract: A deep trench type DRAM cell with shallow trench isolation has a buried polysilicon strap that is defined without the use of a separate mask by depositing the strap material over at least the deep trench before shallow trench definition and using the shallow trench isolation mask to overlap partially the deep trench, thereby defining the strap during the process of cutting the shallow trench.

Abstract: A method for forming a silicide bridge bewteen a diffusion region and an adjacent poly-filled trench separated by a thin dielectric. Silicon is selectively grown over exposed silicon regions under conditions that provide controlled lateral growth over the thin dielectric without also permitting lateral growth over other insulator regions. A refractory metal layer is then deposited and sintered under conditions that limit lateral silicide growth, forming the bridge. This process avoids the random fails produced by previous processes while enhancing the compatibility of bridge formation with shallow junctions, without introducing extra masking steps or other process complexities.