Abstract: The disclosure includes implementations for providing a recommendation to a driver of a second DSRC-equipped vehicle. The recommendation may describe an estimate of how long it would take the second DSRC-equipped vehicle to receive a roadside service from a drive-through business. A method according to some implementations may include receiving, by the second DSRC-equipped vehicle, a Dedicated Short Range Communication message (“DSRC message”) that includes path history data. The path history data may describe a path of a first DSRC-equipped vehicle over a plurality of different times while the first DSRC-equipped vehicle is located in a queue of the drive-through business. The method may include determining delay time data for the second DSRC-equipped vehicle based on the path history data for the first DSRC-equipped vehicle. The delay time data may describe the estimate. The method may include providing the recommendation to the driver. The recommendation may include the estimate.

Abstract: A circuit arrangement includes a preprocessing circuit configured to obtain context information related to a user location, a learning circuit configured to determine a predicted user movement based on context information related to a user location to obtain a predicted route and to determine predicted radio conditions along the predicted route, and a decision circuit configured to, based on the predicted radio conditions, identify one or more first areas expected to have a first type of radio conditions and one or more second areas expected to have a second type of radio conditions different from the first type of radio conditions and to control radio activity while traveling on the predicted route according to the one or more first areas and the one or more second areas.

Abstract: A disclosed apparatus for accomplishing such a task may include (1) a circuit board incorporated into a module designed for insertion into slots of computing devices, (2) at least one conductive contact disposed on the circuit board, (3) a counter circuit disposed on the circuit board and communicatively coupled to the conductive contact, wherein the counter circuit comprises (A) a signal-change detector that detects signal changes as the module is inserted into one of the slots of the computing devices and (B) a counter device that maintains a dynamic count indicative of a number of times that the module has been inserted into one of the slots of the computing devices based at least in part on the signal changes, (4) a battery electrically coupled to the counter circuit, wherein the battery powers the counter device prior to the insertion. Various other apparatuses, systems, and methods are also disclosed.

Abstract: Apparatus and methods for control and calibration of external oscillators are provided herein. In certain embodiments, an electronic oscillator system includes a semiconductor die and a controllable oscillator that is external to the semiconductor die. The oscillation frequency of the controllable oscillator is tuned by a first varactor and a second varactor. The semiconductor die includes a phase-locked loop (PLL) that provides fine tuning to the controllable oscillator by controlling the first varactor, and a calibration circuit that provides coarse tuning to the controllable oscillator by controlling the second varactor.

Abstract: One example embodiment provides one or more of: measuring, via a user equipment (UE), sidelink received signal strength indicator (SL-RSSI) values and sidelink reference signal power received (SL-RSRP) values from a current window of a communication channel shared among a plurality of UEs, excluding a first subset of communication resources from a next window of the communication channel based on the SL-RSSI values in the current window, excluding a second subset of communication resources from the next window of the communication channel based on the SL-RSRP values, and selecting and reserving a resource(s) remaining in the next window of the communication channel after exclusion of the first and second subsets of communication resources from the next window.

Abstract: One example embodiment provides one or more of: measuring, via a user equipment (UE), sidelink received signal strength indicator (SL-RSSI) values and sidelink reference signal power received (SL-RSRP) values from a current window of a communication channel shared among a plurality of UEs, measuring, via the UE, the SL-RSRP values from a frequency-domain and a time-domain of a current window of a communication channel shared among the plurality of UEs, excluding a first subset of communication resources from a next window of the communication channel based on the RSSI values in the current window, excluding a first subset of communication resources from a next window of the communication channel based on the SL-RSRP values from a time-domain, excluding a second subset of communication resources from the next window of the communication channel based on the RSRP values, excluding a second subset of communication resources from the next window of the communication channel based on the SL-RSRP values from a freq

Abstract: Apparatus and methods for multiphase clock generation are provided herein. In certain embodiments, a multiphase clock generator includes a first clock buffer that generates a first output clock signal based on a first input clock signal, a second clock buffer that generates a second output clock signal based on a second input clock signal, and a first clock interpolation circuit that generates a third output clock signal based on interpolating the first input clock signal and the second input clock signal. The first clock interpolation circuit generates the third output clock signal based on multiplying the first input clock signal by a first adjustable current to generate a first multiplied current, multiplying the second input clock signal by a second adjustable current to generate a second multiplied current, combining the first multiplied current and the second multiplied current to generate a combined current, and integrating the combined current.

Abstract: Apparatus and methods for multiphase clock generation are provided herein. In certain embodiments, a multiphase clock generator includes a first clock buffer that generates a first output clock signal based on a first input clock signal, a second clock buffer that generates a second output clock signal based on a second input clock signal, and a first clock interpolation circuit that generates a third output clock signal based on interpolating the first input clock signal and the second input clock signal. The first clock interpolation circuit generates the third output clock signal based on multiplying the first input clock signal by a first adjustable current to generate a first multiplied current, multiplying the second input clock signal by a second adjustable current to generate a second multiplied current, combining the first multiplied current and the second multiplied current to generate a combined current, and integrating the combined current.

Abstract: Methods and systems for verifying a state of a road. The system includes a sensor of a vehicle configured to detect sensor data associated with the road. The system also includes a memory of the vehicle configured to store map data. The system also includes an electronic control unit (ECU) of the vehicle connected to the sensor and configured to determine road data or maneuvering data associated with the road based on the sensor data, and update the map data with the determined road data or maneuvering data.

Abstract: The disclosure describes embodiments for modifying a vehicle component of an ego vehicle based on ranging and misbehavior information determined from digital data included in a Vehicle-to-Everything (V2X) message. In some embodiments, a method includes generating Received Signal Strength (RSS) data describing an RSS value for the V2X message which is originated by a remote vehicle. The method includes determining range data corresponding to the RSS value describing a first range from the ego vehicle to the remote vehicle. The method includes determining that the remote vehicle is providing inaccurate sensor data (an example of misbehavior information) by comparing the first range to a second range which is described by the sensor data which is extracted from the V2X message. The method includes modifying an operation of the vehicle component so that the vehicle component does not consider the sensor data that is provided by the remote vehicle.

Abstract: A disclosed apparatus for accomplishing such a task may include (1) a circuit board incorporated into a module designed for insertion into slots of computing devices, (2) at least one conductive contact disposed on the circuit board, (3) a counter circuit disposed on the circuit board and communicatively coupled to the conductive contact, wherein the counter circuit comprises (A) a signal-change detector that detects signal changes as the module is inserted into one of the slots of the computing devices and (B) a counter device that maintains a dynamic count indicative of a number of times that the module has been inserted into one of the slots of the computing devices based at least in part on the signal changes, (4) a battery electrically coupled to the counter circuit, wherein the battery powers the counter device prior to the insertion. Various other apparatuses, systems, and methods are also disclosed.

Abstract: There is disclosed herein programmable delay lines and control methods having glitch suppression. In particular, the programmable delay lines may include latches that are triggered based on a trigger event of an input signal (which is often an edge of the input signal). The programmable delay lines may include one or more latches coupled between capacitor and transistor subassemblies and the latches, where the latches cause a delay between the time the trigger event arrives at the capacitor and transistor subassemblies and the latches. The delay can prevent the latches from updating at the same time that the edge of the input signal arrives at the capacitor and transistor subassemblies, which can suppress glitches that can causes errors in operation.

Abstract: There is disclosed herein programmable delay lines and control methods having glitch suppression. In particular, the programmable delay lines may include latches that are triggered based on a trigger event of an input signal (which is often an edge of the input signal). The programmable delay lines may include one or more latches coupled between capacitor and transistor subassemblies and the latches, where the latches cause a delay between the time the trigger event arrives at the capacitor and transistor subassemblies and the latches. The delay can prevent the latches from updating at the same time that the edge of the input signal arrives at the capacitor and transistor subassemblies, which can suppress glitches that can causes errors in operation.

Abstract: Described herein are embodiments that provide out-of-band authentication for vehicular communications using Joint Automotive Radar Communications (“JARC” if singular, “JARCs” if plural). A method includes receiving, by a directional radio of a connected vehicle, a directional communication having a payload that includes the first temporary identifier and sensor data for a purported transmitter of the directional communication. The method includes initiating, by the directional radio and a radar of the connected vehicle, a set of JARCs with the purported transmitter to determine an authenticity status of the first temporary identifier. The method includes executing a vehicular action for the payload of the directional communication responsive to the authenticity status.

Abstract: The disclosure includes embodiments for an ego vehicle to detect misbehavior. According to some embodiments, a method includes receiving a V2X message from an attacker. The V2X message includes V2X data describing a location of an object at a target time. The method includes receiving a set of CPMs from a set of remote devices. The set of CPMs include remote sensor data describing a free space region within the roadway environment. The method includes determining a relevant subset of the CPMs include remote sensor data that is relevant to detecting misbehavior. The method includes determining, based at least in part on the remote sensor data of the relevant subset, that the object is not located at the location at the target time. The method includes detecting the misbehavior by the attacker based on the determination that the object is not located at the location at the target time.

Abstract: Systems and methods are provided for optimizing offset compensation in a receiver with multiple offset compensation D/A converters. At each stage where offset cancellation is applied, there is a fan-out of two or more. At the final stage, comparator offset compensation codes are summed and compared against a digital reference. In one version the digital reference is zero. A second implementation has a non-zero digital reference which is the sum of comparator offsets stored from start up. The difference between the sum of offsets and digital reference is applied to a digital accumulator. The most significant bits of the digital accumulator are applied to a digital D/A converter, which cancel analog offsets in an intermediate stage of amplifiers. The summation of offsets feeding into an accumulator is implemented for all preceding stages.

Abstract: A disclosed apparatus for accomplishing such a task may include (1) a circuit board incorporated into a module designed for insertion into slots of computing devices, (2) at least one conductive contact disposed on the circuit board, (3) a counter circuit disposed on the circuit board and communicatively coupled to the conductive contact, wherein the counter circuit comprises (A) a signal-change detector that detects signal changes as the module is inserted into one of the slots of the computing devices and (B) a counter device that maintains a dynamic count indicative of a number of times that the module has been inserted into one of the slots of the computing devices based at least in part on the signal changes, (4) a battery electrically coupled to the counter circuit, wherein the battery powers the counter device prior to the insertion. Various other apparatuses, systems, and methods are also disclosed.

Abstract: Apparatus and methods for phasing detection of asynchronous dividers are provided herein. In certain embodiments, a clock and data recovery system includes a first divider that outputs a first divided clock signal, a second divider that outputs a second divided clock signal, and an asynchronous clock phasing detection circuit that generates a detection signal indicating a relative phase difference between the first divided clock signal and the second divided clock signal. The asynchronous clock phasing detection circuit includes a quantization and logic circuit that generates an output signal indicating when the first divided clock signal and the second divided clock signal are in different states, an oscillator that outputs a control clock signal, a first counter controlled by the control clock signal and configured to count the output signal, and a control circuit that processes a first count signal from the first counter to generate the detection signal.

Abstract: The disclosure describes embodiments for vehicle-to-everything (V2X) data transfer for automated vehicles. In some embodiments, a method includes providing or attempting to provide, by a communication unit of an ego vehicle, digital data to a communication device based on a mode of the communication unit, where the digital data is relayed by the communication device to be received by a server. The method includes determining, by a processor of the ego vehicle, feedback that describes a bandwidth constraint of the communication unit. The method includes modifying, by the processor, the mode based on the feedback so that the mode is consistent with the bandwidth constraint and the digital data is successfully received by the server.

Abstract: There is disclosed herein programmable delay lines and control methods having glitch suppression. In particular, the programmable delay lines may include latches that are triggered based on a trigger event of an input signal (which is often an edge of the input signal). The programmable delay lines may include one or more latches coupled between capacitor and transistor subassemblies and the latches, where the latches cause a delay between the time the trigger event arrives at the capacitor and transistor subassemblies and the latches. The delay can prevent the latches from updating at the same time that the edge of the input signal arrives at the capacitor and transistor subassemblies, which can suppress glitches that can causes errors in operation.