Patents by Inventor John L. McCollum
John L. McCollum has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170179382Abstract: A resistive random access memory device is formed in an integrated circuit between a first metal layer and a second metal layer and includes a first barrier layer disposed over the first metal layer, a tunneling dielectric layer disposed over the first barrier layer, a solid electrolyte layer disposed over the tunneling dielectric layer, an ion source layer disposed over the solid electrolyte layer, and a second barrier layer disposed over the ion source layer.Type: ApplicationFiled: December 9, 2016Publication date: June 22, 2017Applicant: Microsemi SoC CorporationInventors: John L. McCollum, Fethi Dhaoui, Frank W. Hawley
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Publication number: 20170179959Abstract: A low-leakage resistive random access memory cell includes a complementary pair of bit lines and a switch node. A first ReRAM device is connected to a first one of the bit lines. A p-channel transistor has a source connected to the ReRAM device, a drain connected to the switch node, and a gate connected to a bias potential. A second ReRAM device is connected to a second one of the bit lines. An n-channel transistor has a source connected to the ReRAM device a drain connected to the switch node, and a gate connected to a bias potential.Type: ApplicationFiled: December 9, 2016Publication date: June 22, 2017Applicant: Microsemi SoC CorporationInventors: John L. McCollum, Esmat Z. Hamdy
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Patent number: 9520448Abstract: A push-pull resistive random access memory cell circuit includes an output node, a word line, a first bit line, and a second bit line. A first resistive random access memory device is connected between the first bit line and the output node and a second resistive random access memory device is connected between the output node and the second bit line. A first programming transistor has a gate connected to the word line, a drain connected to the output node, and a source. A second programming transistor has a gate connected to the word line, a drain connected to the source of the first programming transistor, and a source. The first and second programming transistors have the same pitch, the same channel length, and the same gate dielectric thickness, the gate dielectric thickness chosen to withstand programming and erase potentials encountered during operation of the push-pull ReRAM cell circuit.Type: GrantFiled: August 10, 2016Date of Patent: December 13, 2016Assignee: Microsemi SoC CorporationInventors: John L. McCollum, Fethi Dhaoui
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Publication number: 20160351626Abstract: A push-pull resistive random access memory cell circuit includes an output node, a word line, a first bit line, and a second bit line. A first resistive random access memory device is connected between the first bit line and the output node and a second resistive random access memory device is connected between the output node and the second bit line. A first programming transistor has a gate connected to the word line, a drain connected to the output node, and a source. A second programming transistor has a gate connected to the word line, a drain connected to the source of the first programming transistor, and a source. The first and second programming transistors have the same pitch, the same channel length, and the same gate dielectric thickness, the gate dielectric thickness chosen to withstand programming and erase potentials encountered during operation of the push-pull ReRAM cell circuit.Type: ApplicationFiled: August 10, 2016Publication date: December 1, 2016Applicant: Microsemi SoC CorporationInventors: John L. McCollum, Fethi Dhaoui
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Patent number: 9484904Abstract: A gate-boosting transmission gate includes an input node and an output node. An n-channel transistor has a first source/drain terminal connected to the input node and a second source/drain terminal connected to the output node, the n-channel transistor having a low threshold. A p-channel transistor has a first source/drain terminal connected to the input node and a second source/drain terminal connected to the output node, the p-channel transistor having a very low threshold.Type: GrantFiled: May 4, 2015Date of Patent: November 1, 2016Assignee: MICROSEMI SOC CORPORATIONInventor: John L. McCollum
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Publication number: 20160269031Abstract: A push-pull resistive random access memory cell circuit includes an output node, a word line, a first bit line, and a second bit line. A first resistive random access memory device is connected between the first bit line and the output node and a second resistive random access memory device is connected between the output node and the second bit line. A first programming transistor has a gate connected to the word line, a drain connected to the output node, and a source. A second programming transistor has a gate connected to the word line, a drain connected to the source of the first programming transistor, and a source. The first and second programming transistors have the same pitch, the same channel length, and the same gate dielectric thickness, the gate dielectric thickness chosen to withstand programming and erase potentials encountered during operation of the push-pull ReRAM cell circuit.Type: ApplicationFiled: January 29, 2016Publication date: September 15, 2016Applicant: Microsemi SoC CorporationInventors: John L. McCollum, Fethi Dhaoui
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Patent number: 9444464Abstract: A push-pull resistive random access memory cell circuit includes an output node, a word line, a first bit line, and a second bit line. A first resistive random access memory device is connected between the first bit line and the output node and a second resistive random access memory device is connected between the output node and the second bit line. A first programming transistor has a gate connected to the word line, a drain connected to the output node, and a source. A second programming transistor has a gate connected to the word line, a drain connected to the source of the first programming transistor, and a source. The first and second programming transistors have the same pitch, the same channel length, and the same gate dielectric thickness, the gate dielectric thickness chosen to withstand programming and erase potentials encountered during operation of the push-pull ReRAM cell circuit.Type: GrantFiled: January 29, 2016Date of Patent: September 13, 2016Assignee: Microsemi SoC CorporationInventors: John L. McCollum, Fethi Dhaoui
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Publication number: 20160204223Abstract: A method for fabricating a high-voltage transistor on a semiconductor substrate includes defining and forming shallow trench isolation regions for all of the transistors, defining and forming well regions for all of the transistors, forming a gate oxide layer in the well regions for all of the transistor, forming gates for all of the transistors over the gate oxide layer, implanting a dopant to form lightly-doped drain regions for all of the transistors, the lightly-doped drain regions for at least drains of the high-voltage transistors being spaced apart from an inner edge of the shallow trench isolation regions, forming gate spacers at sides of the gates of all of the transistors, and implanting a dopant to form sources and drains for all of the transistors, the drains of the high-voltage transistors being formed completely surrounded by the lightly-doped drain regions of the high-voltage transistors.Type: ApplicationFiled: March 21, 2016Publication date: July 14, 2016Applicant: Microsemi SoC CorporationInventors: Fengliang Xue, Fethi Dhaoui, John L. McCollum
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Patent number: 9306573Abstract: A circuit internal to a programmable integrated circuit for preventing laser interrogation of the programmable integrated circuit includes a sense resistor connected between a deep n-well and a source of bias voltage for the deep n-well. A voltage-sensing circuit is coupled across the sense resistor to measure voltage across the sense resistor. A tamper trigger circuit responsive to the voltage sensing circuit generates a tamper signal in response to a voltage sensed in the voltage sensing circuit having a magnitude greater than a threshold value.Type: GrantFiled: July 2, 2015Date of Patent: April 5, 2016Assignee: Microsemi SoC CorporationInventor: John L. McCollum
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Patent number: 9275990Abstract: An integrated circuit is formed on a p-type semiconductor substrate connected to ground potential. A deep n-well is disposed in the p-type substrate. A p-well is disposed in the deep n-well. An n+ drain region and an n+ source region are disposed in the p-well, the n+ source region connected to a common potential. A p-type contact is disposed in the p-well and is connected to ground potential through a resistor.Type: GrantFiled: May 4, 2015Date of Patent: March 1, 2016Assignee: Microsemi SoC CorporationInventors: John L. McCollum, Fethi Dhaoui
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Publication number: 20160020772Abstract: A circuit internal to a programmable integrated circuit for preventing laser interrogation of the programmable integrated circuit includes a sense resistor connected between a deep n-well and a source of bias voltage for the deep n-well. A voltage-sensing circuit is coupled across the sense resistor to measure voltage across the sense resistor. A tamper trigger circuit responsive to the voltage sensing circuit generates a tamper signal in response to a voltage sensed in the voltage sensing circuit having a magnitude greater than a threshold value.Type: ApplicationFiled: July 2, 2015Publication date: January 21, 2016Applicant: Microsemi SoC CorporationInventor: John L. McCollum
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Publication number: 20150365090Abstract: A layout arrangement for a resistive random access memory cell includes an active area, a polysilicon row address line over the active region, a metal column address line running orthogonal to the row address line and having an active region contact portion extending over the active region and having a contact to the active region. A metal output line runs parallel to the column address line over the active region. A first cell contact region intersects with the output line and has a contact to the active region. A first metal cell contact region forms an intersection with the first cell contact region. A first resistive random access memory device is formed at the intersection of the first cell contact region and the output line. A second resistive random access memory device is formed at the intersection of the first cell contact region and the first cell contact region.Type: ApplicationFiled: August 26, 2015Publication date: December 17, 2015Inventors: Jonathan Greene, Frank Hawley, John L. McCollum
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Publication number: 20150318853Abstract: A gate-boosting transmission gate includes an input node and an output node. An n-channel transistor has a first source/drain terminal connected to the input node and a second source/drain terminal connected to the output node, the n-channel transistor having a low threshold. A p-channel transistor has a first source/drain terminal connected to the input node and a second source/drain terminal connected to the output node, the p-channel transistor having a very low threshold.Type: ApplicationFiled: May 4, 2015Publication date: November 5, 2015Applicant: MICROSEMI SOC CORPORATIONInventor: John L. McCollum
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Publication number: 20150318278Abstract: An integrated circuit is formed on a p-type semiconductor substrate connected to ground potential. A deep n-well is disposed in the p-type substrate. A p-well is disposed in the deep n-well. An n+ drain region and an n+ source region are disposed in the p-well, the n+ source region connected to a common potential. A p-type contact is disposed in the p-well and is connected to ground potential through a resistor.Type: ApplicationFiled: May 4, 2015Publication date: November 5, 2015Applicant: MICROSEMI SOC CORPORATIONInventors: John L. McCollum, Fethi Dhaoui
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Patent number: 7486538Abstract: In an integrated circuit, a radiation tolerant static random access memory device comprising a first inverter having an input and an output, a second inverter having an input and an output. A first resistor is coupled between the output of the first inverter and the input of the second inverter. A second resistor is coupled between the output of the second inverter and the input of the first inverter. A first write transistor is coupled to the output of the first inverter and has a gate coupled to a source of a first set of write-control signals and a second write transistor is coupled to the output of the second inverter and has a gate coupled to said source of a second set of write-control signals. Finally, a pass transistor has a gate coupled to the output of on of the first and second inverters.Type: GrantFiled: March 10, 2008Date of Patent: February 3, 2009Assignee: Actel CorporationInventor: John L. McCollum
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Publication number: 20080197450Abstract: A metal-to-metal antifuse having a lower metal electrode, a lower thin adhesion promoting layer disposed over the lower metal electrode, an amorphous carbon antifuse material layer disposed over the thin adhesion promoting layer, an upper thin adhesion promoting layer disposed over said antifuse material layer, and an upper metal electrode. The thin adhesion promoting layers are about 2 angstroms to 20 angstroms in thickness, and are from a material selected from the group comprising SixCy and SixNy. The ratio of x to y in SixCy is in a range of about 1±0.4, and the ratio of x to y in SixNy is in a range of about 0.75±0.225.Type: ApplicationFiled: April 15, 2008Publication date: August 21, 2008Applicants: ACTEL CORPORATION, TEXAS TECH UNIVERSITY SYSTEMInventors: Frank W. Hawley, A. Farid Issaq, John L. McCollum, Shubhra M. Gangopadhyay, Jorge A. Lubguban, Jin Miao Shen
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Patent number: 7366008Abstract: In an integrated circuit, a radiation tolerant static random access memory device comprising a first inverter having an input and an output, a second inverter having an input and an output. A first resistor is coupled between the output of the first inverter and the input of the second inverter. A second resistor is coupled between the output of the second inverter and the input of the first inverter. A first write transistor is coupled to the output of the first inverter and has a gate coupled to a source of a first set of write-control signals and a second write transistor is coupled to the output of the second inverter and has a gate coupled to said source of a second set of write-control signals. Finally, a pass transistor has a gate coupled to the output of on of the first and second inverters.Type: GrantFiled: February 16, 2007Date of Patent: April 29, 2008Assignee: Actel CorporationInventor: John L. McCollum
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Patent number: 7358589Abstract: A metal-to-metal antifuse having a lower metal electrode, a lower thin adhesion promoting layer disposed over the lower metal electrode, an amorphous carbon antifuse material layer disposed over the thin adhesion promoting layer, an upper thin adhesion promoting layer disposed over said antifuse material layer, and an upper metal electrode. The thin adhesion promoting layers are about 2 angstroms to 20 angstroms in thickness, and are from a material selected from the group comprising SixCy and SixNy. The ratio of x to y in SixCy is in a range of about 1+/?0.4, and the ratio of x to y in SixNy is in a range of about 0.75+/?0.225.Type: GrantFiled: August 23, 2005Date of Patent: April 15, 2008Assignee: Actel CorporationInventors: Frank W. Hawley, A. Farid Issaq, John L. McCollum, Shubhra M. Gangopadhyay, Jorge A. Lubguban, Jin Miao Shen
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Patent number: 6965156Abstract: A metal-to-metal antifuse having a lower metal electrode, a lower thin adhesion promoting layer disposed over the lower metal electrode, an amorphous carbon antifuse material layer disposed over the thin adhesion promoting layer, an upper thin adhesion promoting layer disposed over said antifuse material layer, and an upper metal electrode. The thin adhesion promoting layers are about 2 angstroms to 20 angstroms in thickness, and are from a material selected from the group comprising SixCy and SixNy. The ratio of x to y in SixCy is in a range of about 1+/?0.4, and the ratio of x to y in SixNy is in a range of about 0.75+/?0.225.Type: GrantFiled: December 27, 2002Date of Patent: November 15, 2005Assignees: Actel Corporation, Texas Tech University SystemInventors: Frank W. Hawley, A. Farid Issaq, John L. McCollum, Shubhra M. Gangopadhyay, Jorge A. Lubguban, Jin Miao Shen
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Publication number: 20030205723Abstract: A metal-to-metal antifuse is disposed between two metal interconnect layers in an integrated circuit. An insulating layer is disposed above a lower metal interconnect layer. The insulating layer includes a via formed therethrough containing a tungsten plug in electrical contact with the lower metal interconnect layer. The tungsten plug forms a lower electrode of the antifuse. The upper surface of the tungsten plug is planarized with the upper surface of the insulating layer. In a first embodiment, an antifuse material layer comprising amorphous carbon, amorphous carbon doped with hydrogen or fluorine, or amorphous silicon carbide is disposed above the upper surface of the tungsten plug. A layer of a barrier metal disposed over the antifuse material layer forms an upper electrode of the antifuse. An oxide or tungsten hard mask provides high etch selectivity and the possibility to etch barrier metals without affecting the dielectric constant value and mechanical properties of the antifuse material.Type: ApplicationFiled: April 1, 2003Publication date: November 6, 2003Inventors: Frank W. Hawley, John L. McCollum, Jeewika C. Ranaweera