Abstract: An antifuse may be fabricated as a part of an integrated circuit in a layer located above and insulated from the semiconductor substrate. The antifuse includes a lower first metal electrode, a first antifuse dielectric layer, preferably silicon nitride, disposed on the lower first electrode and an antifuse layer, preferably amorphous silicon, disposed on the first dielectric layer. An inter-layer dielectric layer is disposed on the antifuse layer and includes an antifuse via formed completely therethrough. A second antifuse dielectric layer, preferably silicon nitride, is disposed over the amorphous silicon layer in the antifuse via, and an upper second metal electrode is disposed over the second dielectric layer in the antifuse via.

Abstract: A programmable interface for selectively making connections between an output node of a logic module and an interconnection array in a field programmable gate array integrated circuit includes a first antifuse having a first electrode electrically connected to the output node and a second electrode connected to the first electrode of a second a second antifuse. The second electrode or the second antifuse is connected to the interconnection array. A high-voltage transistor, capable of withstanding programming voltages used in the integrated circuit to program the antifuses, is connected between the common connection comprising the second electrode of the first antifuse and the first electrode of the second antifuse and a fixed voltage potential such as ground. A control element of the high-voltage transistor is connected to circuitry for programming antifuses.

Abstract: Apparatus for measuring the resistance of a programmed antifuse in an integrated circuit is integrated on the same integrated circuit as the antifuse and is controlled by a programming circuit disposed on an integrated circuit and comprises a first voltage sensing transistor having a first drain/source electrically connected to a first I/O pad, a gate electrically connected to the programming circuit, and a second drain/source electrically connected to a first electrode of the antifuse, and a second voltage sensing transistor having a first drain/source electrically connected to a second I/O pad, a gate electrically connected to the programming circuit, and a second drain/source electrically connected to a second electrode of the antifuse.

Abstract: A process for fabricating the metal-to-metal antifuse of the present invention includes the steps of forming a first metal layer on a semiconductor or other microcircuit structure; forming a first barrier layer over the first metal layer; forming a thick insulating layer over the barrier layer; forming an antifuse aperture in the thick insulating layer; forming a first heavily doped amorphous silicon layer in the aperture over the first barrier layer; forming a dielectric antifuse material layer over the first amorphous silicon layer; forming a second heavily doped amorphous silicon layer over the first dielectric antifuse material layer; forming a second barrier layer over the second amorphous silicon layer; and forming a second metal layer over the second barrier layer.

Abstract: A field programmable, digital signal processing integrated circuit is formed in a semiconductor die and includes an array of arithmetic logic (ALU) circuits. A user programmable interconnect architecture is superimposed on the array of ALU circuits. One or more interface circuits comprising digital-to-analog (D/A) converters or analog-to-digital (A/D) converters are provided on the integrated circuit to interface to off-chip analog input signals and provide off-chip analog output signals. Circuitry is provided to program the interconnections between the interface circuits and the ALU circuits and between individual ones of the ALU circuits, as well as to define the specific functions of the individual ALU circuits.

Abstract: Apparatus for measuring the resistance of a programmed antifuse in an integrated circuit is integrated on the same integrated circuit as the antifuse and is controlled by a programming circuit disposed on an integrated circuit and comprises a first voltage sensing transistor having a first drain/source electrically connected to a first I/O pad, a gate electrically connected to the programming circuit, and a second drain/source electrically connected to a first electrode of the antifuse, and a second voltage sensing transistor having a first drain/source electrically connected to a second I/O pad, a gate electrically connected to the programming circuit, and a second drain/source electrically connected to a second electrode of the antifuse.

Abstract: Electrically-programmable low-impedance antifuses are disclosed having capacitor-like structure with very low leakage before programming and a low resistance after programming. The antifuses of the present invention include a first conductive electrode which may be formed as a diffusion region in a semiconductor substrate or may be formed from a semiconductor material, such as polysilicon, located above and insulated from the substrate. A dielectric layer is disposed over the first electrode. A second electrode is formed over the dielectric layer from a semiconductor material such as polysilicon, or metal having a barrier metal underneath. At least one of the two electrodes of each antifuse is highly-doped or implanted with arsenic such that high concentrations of arsenic exist at the interface between the electrode and the dielectric layer.

Abstract: An antifuse may be fabricated as a part of an integrated circuit in a layer located above and insulated from the semiconductor substrate. The antifuse includes a lower first electrode, a first dielectric layer disposed over the lower first electrode, a layer of amorphous silicon disposed above the first dielectric layer, a second dielectric layer disposed above the amorphous silicon layer, and an upper second electrode disposed above the second dielectric layer.

Abstract: A metal-to metal antifuse device is provided in a double layer metal interconnect structure. A lower electrode comprises a first multilayer metal layer interconnect disposed on an insulator. An inter-metal dielectric is disposed on the first metal layer interconnect having an antifuse via. An antifuse material layer is disposed in the antifuse via and having an upper electrode comprising a second multilayer metal layer interconnect.

Abstract: A metal-to-metal antifuse includes a lower electrode formed from a first metal layer in a semiconductor or other microcircuit structure. A barrier layer is disposed over the first metal layer. A first heavily-doped amorphous silicon layer is disposed over the barrier layer. A thin dielectric antifuse material is disposed over the first amorphous silicon layer. This dielectric can be nearly any dielectric such as nitride or oxide or a combination of these materials such as ONO and should have a breakdown voltage suitable for programming inside the integrated circuit. A second heavily-doped amorphous silicon layer is disposed over the dielectric layer. An upper electrode, comprising a second metal layer including an underlying barrier layer, is disposed over the second amorphous silicon layer. The first and second metal layers may comprise metal interconnect layers in the circuit structure.

Abstract: An isolation conductor is provided between a first conductor and a plurality of second conductors to which potential connections can be made from the first conductor. An isolation antifuse is connected between the first conductor and the isolation conductor. Individual antifuses are connected between the isolation bus and each of the plurality of second conductors. A pull-down or pullup transistor is connected between the isolation conductor and a selected circuit node to allow programming of the isolation antifuse and an isolation transistor may be connected between the first conductor and the isolation conductor to allow testing of the isolation conductor.

Abstract: A process for fabricating a metal-to-metal antifuse in a process sequence for forming a double layer metal interconnect structure includes the steps of forming and defining a first metal interconnect layer, forming and planarizing an inter-metal dielectric layer, forming an antifuse cell opening in the inter-metal dielectric layer, forming and defining an antifuse layer, forming metal-to-metal via holes in the inter-metal dielectric layer, and forming and defining a second metal interconnect layer.

Abstract: A user-configurable circuit architecture includes a two dimensional array of functional circuit modules disposed within a semiconductor substrate. A first interconnect layer disposed above and insulated from the semiconductor substrate contains a plurality of conductors and is used for internal connections within the functional circuit modules. A second interconnect layer disposed above and insulated from the first interconnect layer contains a plurality of segmented tracks of conductors running in a first direction and is used to interconnect functional circuit module inputs and outputs. A third interconnect layer disposed above and insulated from the second interconnect layer contains a plurality of segmented tracks of conductors running in a second direction, some of the segments of conductors forming intersections with ones of the segments of the conductors in the second interconnect layer, and is used to interconnect functional circuit module inputs and outputs to implement the desired applications.

Abstract: A user-configurable circuit architecture includes a two dimensional array of functional circuit modules disposed within a semiconductor substrate. A first interconnect layer disposed above and insulated from the semiconductor substrate contains a plurality of conductors and is used for internal connections within the functional circuit modules. A second interconnect layer disposed above and insulated from the first interconnect layer contains a plurality of segmented tracks of conductors running in a first direction and is used to interconnect functional circuit module inputs and outputs. A third interconnect layer disposed above and insulated from the second interconnect layer contains a plurality of segmented tracks of conductors running in a second direction, some of the segments of conductors forming intersections with ones of the segments of the conductors in the second interconnect layer, and is used to interconnect functional circuit module inputs and outputs to implement the desired applications.

Abstract: A structure used to protect a dielectric is disclosed wherein a transistor located nearby the dielectric is connected in series with a conductor overlying the fragile dielectric such that the transistor gate will accumulate charge along with the conductive material over the fragile dielectric. After fabrication and during normal circuit operation, this transistor device remians in an off state, isolating the fragile dielectric node from other circuitry. In an alternate embodiment the protection transistor is a floating gate depletion device, which would always be on until the circuit is activated. At the time the circuit is activated, the device is turned off by trapping electrons on the gate by avalanching a junction associated with it. In a preferred embodiment, a buried contact if formed after the conductor overlying the dielectric, usually polysilicon, is formed. This buried contact connects the conductor to the discharging transistor.

Abstract: An electrically programmable antifuse element incorporates a composite interlayer of dielectric material and amorphous silicon interposed between two electrodes. The lower electrode may be formed from a refractory metal such as tungsten. Preferably, a thin layer of titanium is deposited over the tungsten layer and its surface is then oxidized to form a thin layer of titanium oxide which serves as the dielectric material of the composite dielectric/amorphous silicon interlayer. A layer of amorphous silicon is then deposited on top of the titanium oxide dielectric to complete the formation of the composite interlayer. A topmost layer of a refractory metal such as tungsten is then applied over the amorphous silicon to form the topmost electrode of the antifuse.

Abstract: A minimum sized aperture for a reduced capacitance anti-fuse or other structure may be formed by birds beak encroachment of thick oxide under a masking layer or by isotropic etching of a masking layer followed by birds beak encroachment of thick oxide.

Abstract: A structure used to protect a dielectric is disclosed wherein a transistor located nearby the dielectric is connected in series with a conductor overlying the fragile dielectric such that the transistor gate will accumulate charge along with the conductive material over the fragile dielectric. After fabrication and during normal circuit operation, this transistor device remains in an off state, isolating the fragile dielectric node from other circuitry. In an alternate embodiment the protection transistor is a floating gate depletion device, which would always be on until the circuit is activated. At the time the circuit is activated, the device is turned off by trapping electrons on the gate by avalancing a junction associated with it. In a preferred, embodiment, a buried contact is formed after the conductor overlying the dielectric, usually polysilicon, is formed. This buried contact connects the conductor to the discharging transistor.

Abstract: A programmable low impedance interconnect diode element is disclosed having a lower electrode formed of a semiconductor material of a first conductivity type covered by an insulating dielectric layer which may be in a preferred embodiment comprised of an initial layer of silicon dioxide, a second layer of silicon nitride and a third layer of silicon dioxide, covered by a layer of semiconductor material of a second conductivity type.A programmable read only memory array and a programmable logic array comprising a plurality of the above-described cells are also disclosed.

Abstract: A programmable low impedance interconnect diode element is disclosed having a lower electrode formed of a semiconductor material of a first conductivity type covered by an insulating dielectric layer which may be in a preferred embodiment comprised of an initial layer of silicon dioxide, a second layer of silicon nitride and a third layer of silicon dioxide, covered by a layer of semiconductor material of a second conductivity type.A programmable read only memory array and a programmable logic array comprising a plurality of the above-described cells are also disclosed.