Abstract: A metal-to-metal antifuse is disposed between two metal interconnect layers in an integrated circuit. An insulating layer is disposed above a lower metal interconnect layer. The insulating layer includes a via formed therethrough containing a tungsten plug in electrical contact with the lower metal interconnect layer. The tungsten plug forms a lower electrode of the antifuse. The upper surface of the tungsten plug is planarized with the upper surface of the insulating layer. In a first embodiment, an antifuse material layer comprising amorphous carbon, amorphous carbon doped with hydrogen or fluorine, or amorphous silicon carbide is disposed above the upper surface of the tungsten plug. A layer of a barrier metal disposed over the antifuse material layer forms an upper electrode of the antifuse. An oxide or tungsten hard mask provides high etch selectivity and the possibility to etch barrier metals without affecting the dielectric constant value and mechanical properties of the antifuse material.

Abstract: An antifuse comprises a lower electrode formed from a metal layer in a microcircuit. A interlayer dielectric layer is disposed over the lower electrode and has an aperture formed therein. A conductive plug, formed from a material such as tungsten, is formed in the aperture. The upper surface of the interlayer dielectric is etched back to create a raised portion of the plug. The upper edges of the plug are rounded. An antifuse layer, preferably comprising a silicon nitride, amorphous silicon, silicon nitride sandwich incorporating a thin silicon dioxide layer above or below the amorphous silicon layer or such a sandwich structure covered by a titanium nitride layer, is disposed above the plug. An upper electrode, preferably comprising a metal layer is disposed over the antifuse layer.

Abstract: An antifuse comprises a lower electrode formed from a metal layer in a microcircuit. A interlayer dielectric layer is disposed over the lower electrode and has an aperture formed therein. A conductive plug, formed from a material such as tungsten, is formed in the aperture. The upper surface of the interlayer dielectric is etched back to create a raised portion of the plug. The upper edges of the plug are rounded. An antifuse layer, preferably comprising a silicon nitride, amorphous silicon, silicon nitride sandwich incorporating a thin silicon dioxide layer above or below the amorphous silicon layer or such a sandwich structure covered by a titanium nitride layer, is disposed above the plug. An upper electrode, preferably comprising a metal layer is disposed over the antifuse layer.

Abstract: An antifuse comprises an antifuse material disposed between a lower conductive electrode and an upper conductive electrode. The antifuse material comprises a layer of amorphous silicon disposed between two layers of silicon nitride. A thin layer of silicon dioxide is disposed between the layer of amorphous silicon and one of the silicon nitride layers.

Abstract: A metal-to-metal antifuse disposed between two aluminum metallization layers in a CMOS integrated circuit or similar structure includes an antifuse material layer having a substantially aluminum-free conductive link. The substantially aluminum-free link is formed by forming a first barrier metal layer out of TiN having a first thickness, a second barrier metal layer out of TiN having a second thickness which may be less than said first thickness, the first and second barrier metal layers separating the antifuse material layer from first and second electrodes. The antifuse is programmed by applying a voltage potential capable of programming the antifuse across the electrodes with the more positive side of the potential applied to the electrode adjacent the barrier metal layer having the least thickness.

Abstract: An antifuse comprises a lower electrode formed from a metal layer in a microcircuit. A interlayer dielectric layer is disposed over the lower electrode and has an aperture formed therein. A conductive plug, formed from a material such as tungsten, is formed in the aperture. The upper surface of the interlayer dielectric is etched back to create a raised portion of the plug. The upper edges of the plug are rounded. An antifuse layer, preferably comprising a silicon nitride, amorphous silicon, silicon nitride sandwich incorporating a thin silicon dioxide layer above or below the amorphous silicon layer or such a sandwich structure covered by a titanium nitride layer, is disposed above the plug. An upper electrode, preferably comprising a metal layer is disposed over the antifuse layer.

Abstract: An antifuse based PROM cell design allows large currents to be sinked during cell programming to ensure low programmed resistance of the cell while using minimum-geometry select devices. This is achieved by utilizing a pseudo SCR latchup effect during programming. The regions in the semiconductor substrate forming lower antifuse electrodes for the antifuses in the PROM cells are doped at low levels with phosphorus. An antifuse layer formed from an oxide, oxide-nitride, or oxide-nitride-oxide antifuse layer, is formed over the lower antifuse electrode, and an upper antifuse electrode is formed from polysilicon. A minimum-geometry N-Channel select transistor is formed in series with the antifuse to complete the PROM cell. The drain and source diffusions of the select transistor are arsenic doped and the drain diffusion is contiguous with the lower antifuse electrode. A bit line is contacted to the upper antifuse electrode and the select transistor gate is part of a polysilicon word line.

Abstract: An antifuse comprises a substantially planar conductive lower electrode covered by a first layer of silicon nitride. A layer of amorphous silicon is disposed over the silicon nitride layer. A first dielectric layer is disposed over the surface of the amorphous silicon layer and has a first aperture therethrough communicating with the amorphous silicon layer. A second layer of silicon nitride is disposed over the first dielectric layer and in the first aperture. A conductive upper electrode, such as a layer of titanium nitride, is disposed over the second layer of silicon nitride. A second dielectric layer is disposed over the surface of the conductive upper electrode and has a second aperture therethrough in alignment with the first aperture communicating with the conductive upper electrode. An overlying metal layer is disposed over the surface of the second dielectric layer and in the second aperture making electrical contact with the conductive upper electrode.

Abstract: The area of the switching devices for programming metal-to-metal antifuses can be drastically reduced by employing bipolar devices or the bipolar effects of SCR type switches to pass large currents while utilizing the minimum amount of die area. The switching devices may be formed in both p-type and n-type substrates. In a first antifuse programming structure fabricated on a p-type substrate, an NPN bipolar transistor is used as a pullup device and an SCR is used as a pulldown device. In a second antifuse programming structure, SCR devices are used as both pullup and pulldown devices. In a third antifuse programming structure fabricated on a p-type substrate, an NPN bipolar transnsistor is used as a pullup device and a PNP bipolar transistor is used as a pulldown device. In a fourth antifuse programming structure fabricated on a p-type substrate, an NPN bipolar transistor is used as a pullup device and a N-channel MOS transistor is used as a pulldown device.

Abstract: An antifuse comprises a lower electrode formed from a metal layer in a microcircuit. A interlayer dielectric layer is disposed over the lower electrode and has an aperture formed therein. A conductive plug, formed from a material such as tungsten, is formed in the aperture. The upper surface of the interlayer dielectric is etched back to create a raised portion of the plug. The upper edges of the plug are rounded. An antifuse layer, preferably comprising a silicon nitride, amorphous silicon, silicon nitride sandwich incorporating a thin silicon dioxide layer above or below the amorphous silicon layer or such a sandwich structure covered by a titanium nitride layer, is disposed above the plug. An upper electrode, preferably comprising a metal layer is disposed over the antifuse layer.

Abstract: According to the present invention, an antifuse comprises first and second conductors separated by an antifuse material having a thickness selected to impart a desired target programming voltage to the antifuse. The antifuse material is of SiC and provides a solid material stable at temperatures below about 350.degree. C., a resistivity of greater than about 10.sup.12 ohm-cm. The antifuse material may be applied using chemical vapor deposition (CVD) techniques. Also, the SiC antifuse material of the present invention may take any one of a number of via antifuse and stacked antifuse forms.

Abstract: According to a first aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer under a plug of an electrically conductive material disposed between two metallization layers. According to a second aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer comprising a first nitride/first amorphous silicon/second nitride/second amorphous silicon sandwich under a plug of an electrically conductive material lined with titanium disposed between two metallization layers. In this aspect of the invention the titanium is allowed to react with the second amorphous silicon layer to form an electrically conductive silicide. This leaves the first nitride/first amorphous silicon/second nitride as the antifuse material layer while guaranteeing a strict control on the thickness of the antifuse material layer for assuring strict control over its respective breakdown or programming voltage.

Abstract: An antifuse may be fabricated as a part of an integrated circuit in a layer located above and insulated from the semiconductor substrate. The antifuse includes a lower first metal electrode, a first antifuse dielectric layer, preferably silicon nitride, disposed on the lower first electrode and an antifuse layer, preferably amorphous silicon, disposed on the first dielectric layer. An inter-layer dielectric layer is disposed on the antifuse layer and includes an antifuse via formed completely therethrough. A second antifuse dielectric layer, preferably silicon nitride, is disposed over the amorphous silicon layer in the antifuse via, and an upper second metal electrode is disposed over the second dielectric layer in the antifuse via.

Abstract: An antifuse includes an antifuse material disposed between a lower conductive electrode and an upper conductive electrode. The antifuse material includes a layer of amorphous silicon disposed between two layers of silicon nitride. A thin layer of silicon dioxide is disposed between the layer of amorphous silicon and one of the silicon nitride layers.

Abstract: According to a first aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer under a plug of an electrically conductive material disposed between two metallization layers. According to a second aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer comprising a first nitride/first amorphous silicon/second nitride/second amorphous silicon sandwich under a plug of an electrically conductive material lined with titanium disposed between two metallization layers. In this aspect of the invention the titanium is allowed to react with the second amorphous silicon layer to form an electrically conductive silicide. This leaves the first nitride/first amorphous silicon/second nitride as the antifuse material layer while guaranteeing a strict control on the thickness of the antifuse material layer for assuring strict control over its respective breakdown or programming voltage.

Abstract: A metal-to-metal antifuse disposed between two aluminum metallization layers in a CMOS integrated circuit or similar structure includes an antifuse material layer having an aluminum-free conductive link. The aluminum-free link is formed by forming a first barrier metal layer out of TiN having a first thickness, a second barrier metal layer out of TiN having a second thickness which may be less than said first thickness, the first and second barrier metal layers separating the antifuse material layer from first and second electrodes. The antifuse is programmed by applying a voltage potential capable of programming the antifuse across the electrodes with the more positive side of the potential applied to the electrode adjacent the barrier metal layer having the least thickness.

Abstract: In an antifuse and metal interconnect structure in an integrated circuit a substrate has an insulating layer disposed on an upper surface, a first multilayer metal interconnect layer disposed on the insulating layer, and having a first portion forming a lower antifuse electrode and a second portion forming a lower metal interconnect electrode wherein the first portion includes an upper barrier metal layer. An inter-metal dielectric layer is disposed on the lower antifuse and metal interconnect electrodes wherein the inter-metal dielectric layer includes an antifuse via formed therethrough and communicating with said lower antifuse electrode, and a metal interconnect via former therethrough communicating with the lower metal interconnect electrode, An antifuse material layer is disposed in the antifuse via, and a second multilayer metal interconnect layer is disposed on the antifuse material layer and in the upper metal interconnect electrode via and on the lower metal interconnect electrode.

Abstract: According to a first aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer under a plug of an electrically conductive material disposed between two metallization layers, According to a second aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer comprising a first nitride/first amorphous silicon/second nitride/second amorphous silicon sandwich under a plug of an electrically conductive material lined with titanium disposed between two metallization layers. In this aspect of the invention the titanium is allowed to react with the second amorphous silicon layer to form an electrically conductive silicide. This leaves the first nitride/first amorphous silicon/second nitride as the antifuse material layer while guaranteeing a strict control on the thickness of the antifuse material layer for assuring strict control over its respective breakdown or programming voltage.

Abstract: An antifuse comprises first and second electrodes separated by an antifuse material having a thickness selected to impart a desired target programming voltage to the antifuse. The antifuse material comprises a solid material stable at temperatures below about 600.degree. C., having a defect density less than about 100 defects/cm.sup.2, a breakdown field less than about 10 megavolts/cm, a dielectric constant lower than about 4.0, a resistivity of greater than about 10.sup.4 ohm-cm. The antifuse material may comprise organic materials such as polyimides compatible with high-temperature processes including cured polyamic acids, pre-imidazed polymers, photo-sensitive polyimides, and other polimides such as pyralin, probimide, PIQ, etc. The antifuse materials of the present invention also include fluorinated polymers having very low dielectric constants, such as teflon, paralines, polyphenylquinoxaline, benzocyclobutene polymers, and perfluoropolymers.

Abstract: A field programmable, digital signal processing integrated circuit is formed in a semiconductor die and includes an array of arithmetic logic (ALU) circuits. A user programmable interconnect architecture is superimposed on the array of ALU circuits. One or more interface circuits comprising digital-to-analog (D/A) converters or analog-to-digital (A/D) converters are may be provided on the integrated circuit to interface to off-chip analog input signals and provide off-chip analog output signals. Circuitry is provided to program the interconnections between the interface circuits and the ALU circuits and between individual ones of the ALU circuits, as well as to define the specific functions of the individual ALU circuits.