Abstract: Product chips and die, methods for fabricating product chips, and methods for tracking the identity of die after singulation from a wafer. The product chips and die include a pattern of features formed in a metallization level of a back-end-of-line (BEOL) wiring structure. The features in the pattern contain information relating to the die, such as a unique identifier that includes a wafer identification for a wafer used to fabricate the die and a product chip location for the die on the wafer. The features may be imaged with the assistance of a beam of electromagnetic radiation that penetrates into a packaged die and is altered by the presence of the features in a way that promotes imaging.

Abstract: Methods for tracking the identity of die after singulation from a wafer. The product chips and die include a pattern of features formed in a metallization level of a back-end-of-line (BEOL) wiring structure. The features in the pattern contain information relating to the die, such as a unique identifier that includes a wafer identification used to fabricate the die and a product chip location for the die on a wafer. The features may be imaged with the assistance of a beam of electromagnetic radiation that penetrates into a packaged die and is altered by the presence of the features in a way that promotes imaging.

Abstract: Product chips and die that include a pattern of features formed in a metallization level of a back-end-of-line (BEOL) wiring structure. The features in the pattern contain information relating to the die, such as a unique identifier that includes a wafer identification used to fabricate the die and a product chip location for the die on a wafer. The features may be imaged with the assistance of a beam of electromagnetic radiation that penetrates into a packaged die and is altered by the presence of the features in a way that promotes imaging.

Abstract: In a first aspect, an inventive apparatus for imaging a chip on a wafer includes a combined diamond chip image and kerf image having a plurality of sloped sides. The combined diamond chip image and kerf image includes a diamond chip image comprising a plurality of chip image rows that are parallel to at least one diagonal of the diamond chip image, and includes a kerf image adjacent to the diamond chip image. The kerf image comprises at least one kerf image row that is parallel to the at least one diagonal of the diamond chip image. The apparatus further includes a blocking material extending from the combined diamond chip image and kerf image to at least a periphery of an exposure field of a stepper. In a second aspect the imaging apparatus comprises an n-sided polygon-shaped combined chip image and kerf image. Also provided are inventive methods of manufacturing chips, and wafers manufactured in accordance with the inventive methods.

Abstract: Methods for modeling a random variable with spatially inhomogenous statistical correlation versus distance, standard deviation, and mean by spatial interpolation with statistical corrections. The method includes assigning statistically independent random variable to a set of seed points in a coordinate frame and defining a plurality of test points at respective spatial locations in the coordinate frame. A equation for a random variable is determined for each of the test points by spatial interpolation from one or more of the random variable assigned to the seed points. The method further includes adjusting the equation of the random variable at each of the test point with respective correction factor equations.

Abstract: A method for designing a chip a priori for design subsetting, feature analysis, and yield learning. The method includes identifying a plurality of signal paths within a chip design that can be readily identified from chip fail data and removing a fraction of the plurality of signal paths that have physical design constraints to generate a subset of the plurality of signal paths. The method further includes constructing a physical implementation of each of the signal paths in the subset, identifying one or more signal paths in the subset that are not constructed consistently with the respective physical implementation, and removing those signal paths from the subset.

Abstract: Product chips and die, methods for fabricating product chips, and methods for tracking the identity of die after singulation from a wafer. The product chips and die include a pattern of features formed in a metallization level of a back-end-of-line (BEOL) wiring structure. The features in the pattern contain information relating to the die, such as a unique identifier that includes a wafer identification for a wafer used to fabricate the die and a product chip location for the die on the wafer. The features may be imaged with the assistance of a beam of electromagnetic radiation that penetrates into a packaged die and is altered by the presence of the features in a way that promotes imaging.

Abstract: A circuit layout methology is provided for eliminating the extra processing time and file-space requirements associated with the optical proximity correction (OPC) of a VLSI design. The methodology starts with the design rules for a given manufacturing technology and establishes a new set of layer-specific grid values. A layout obeying these new grid requirements leads to a significant reduction in data preparation time, cost, and file size. A layout-migration tool can be used to modify an existing layout in order to enforce the new grid requirements.

Abstract: The invention provides a method for providing an integrated circuit (6) having a substantially uniform density between parts (10, 12, 14 and 16) of the IC that are non-orthogonally angled. In particular, the invention provides fill tiling patterns (32, 34) oriented substantially parallel to electrical structure regardless of their angle. A method of electrical analysis based on this provision is also provided as is a related program product.

Abstract: Disclosed are embodiments of a method, service, and computer program product for performing yield-aware IC routing for a design. The method performs an initial global routing which satisfies wiring congestion constraints. Next, the method performs wire spreading and wire widening on the global route, layer by layer, based on, for example, a quadratic congestion optimization. Following this, timing closure is performed on the global route using results of the wire spreading and wire widening. Post-routing wiring width and wire spreading adjustments are made using the critical area yield model. In addition, the method allows for the optimization of already-routed data.

Abstract: Disclosed are embodiments of a method, service, and computer program product for performing yield-aware IC routing for a design. The method performs an initial global routing which satisfies wiring congestion constraints. Next, the method performs wire spreading and wire widening on the global route, layer by layer, based on, for example, a quadratic congestion optimization. Following this, timing closure is performed on the global route using results of the wire spreading and wire widening. Post-routing wiring width and wire spreading adjustments are made using the critical area yield model. In addition, the method allows for the optimization of already-routed data.

Abstract: A system and method of providing error detection and correction capability in an IC using redundant logic cells and an embedded field programmable gate array (FPGA). The system and method provide error correction (EC) to enable a defective logic function implemented within an IC chip design to be replaced, wherein at least one embedded FPGA is provided in the IC chip to perform a logic function. If a defective logic function is identified in the IC design, the embedded FPGA is programmed to correctly perform the defective logic function. All inputs in an input cone of logic of the defective logic function are identified and are directed into the embedded FPGA, such that the embedded FPGA performs the logic function of the defective logic function.

Abstract: An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.

Abstract: A method for designing a chip a priori for design subsetting, feature analysis, and yield learning. The method includes identifying a plurality of signal paths within a chip design that can be readily identified from chip fail data and removing a fraction of the plurality of signal paths that have physical design constraints to generate a subset of the plurality of signal paths. The method further includes constructing a physical implementation of each of the signal paths in the subset, identifying one or more signal paths in the subset that are not constructed consistently with the respective physical implementation, and removing those signal paths from the subset.

Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

Abstract: A system and method for diagnosing a failure in an electronic device. A disclosed system comprises: a defect table that associates previously studied features with known failures; and a fault isolation system that compares an inputted set of suspected faulty device features with the previously studied features listed in the defect table in order to identify causes of the failure.

Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

Abstract: The invention provides a method, system, and program product for diagnosing an integrated circuit. In particular, the invention captures one or more images for each relevant circuit layer of the integrated circuit. Based on the image(s), a component netlist is generated. Further, a logic netlist is generated by applying hierarchical composition rules to the component netlist. The component netlist and/or logic netlist can be compared to a reference netlist to diagnose the integrated circuit. The invention can further generate a schematic based on the component netlist or logic netlist in which components are arranged according to port, power, and/or component pin connection information determined from the netlist. Further, the schematic can be displayed in a manner that wiring connections are selectively displayed to assist a user in intelligently arranging the circuit components.

Abstract: An electrical wiring structure and a computer system for designing the electrical wiring structure. The electrical wiring structure includes a wire pair. The wire pair includes a first wire and a second wire. The second wire is slated for being tri-stated. The wire pair has a same-direction switching probability ?SD per clock cycle that is no less than a pre-selected minimum same-direction switching probability ?SD,MIN or has an opposite-direction switching probability ?OD per clock cycle that is no less than a pre-selected minimum opposite-direction switching probability ?OD,MIN. The first wire and the second wire satisfies at least one mathematical relationship involving LCOMMON and WSPACING, where WSPACING is defined as a spacing between the first wire and the second wire, and LCOMMON is defined as a common run length of the first wire and the second wire.

Abstract: A system and method of providing error detection and correction capability in an IC using redundant logic cells and an embedded field programmable gate array (FPGA). The system and method provide error correction (EC) to enable a defective logic function implemented within an IC chip design to be replaced, wherein at least one embedded FPGA is provided in the IC chip to perform a logic function. If a defective logic function is identified in the IC design, the embedded FPGA is programmed to correctly perform the defective logic function. All inputs in an input cone of logic of the defective logic function are identified and are directed into the embedded FPGA, such that the embedded FPGA performs the logic function of the defective logic function.