Patents by Inventor John McCormick
John McCormick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6023420Abstract: A three-phase inverter for small, high speed motors such as a miniature centrifical compressor which has a low voltage, high current requirement. The inverter is supplied with DC power at 28 volts, and produces power of about 50 to 500 watts at about 15 volts, and at frequencies of about 5 to 9 kilohertz. Six D-type flip-flops with clock inputs produce twelve signals which are provided to six bridge drivers. Each bridge driver controls two MOSFET's in series. The MOSFET's are supplied with DC power. Outputs are fed to primaries of adjacent transformers in a circular array. The transformer secondaries are arranged in a star configuration to produce stepped voltage and saw-tooth current output wave forms approximating sinusoids in three phases.Type: GrantFiled: November 17, 1998Date of Patent: February 8, 2000Assignee: Creare, Inc.Inventors: John A. McCormick, Javier A. Valenzuela
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Patent number: 6011992Abstract: A system for measuring changes in the resistance of a living body includes a resistance measuring circuit, an amplifier circuit and an indicator circuit in which the amplifier circuit includes a calibration circuit to give a generally constant amplitude response to a given measured input. Radio frequency insulators are included to reduce noise in the system. The circuits are operated such that when an overall change in the resistance of a living body occurs, the resistance measuring circuit is adjusted to determine the overall resistance. To account for changes in sensitivity caused by the overall change in resistance, the gain of the amplifier circuit is automatically adjusted to thereby maintain a generally constant amplitude response.Type: GrantFiled: May 9, 1996Date of Patent: January 4, 2000Assignee: Church of Spirtual TechnologyInventors: Lafayette Ron Hubbard, deceased, by Norman F. Starkey, legal representative, John McCormick, James Stavropoulos, Richard Stinnett
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Patent number: 6008991Abstract: An electronic system such as a Board-Level-Product (BLP) includes at least one integrated circuit device which is mounted on a circuit board. Each integrated circuit device includes a thin dielectric substrate bearing a plurality of conductive leads and has a hole circumscribed by the substrate in which is positioned a die having pads that are bonded to ends of leads carried by the substrate and projecting into the hole for contact with the die pads. The leads include free outer ends that project laterally outwardly and downwardly away from the plane of the substrate for connection to contact pads on the circuit board.Type: GrantFiled: July 24, 1997Date of Patent: December 28, 1999Assignee: LSI Logic CorporationInventors: Emily Hawthorne, John McCormick
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Patent number: 5898575Abstract: A thin dielectric substrate bearing a plurality of conductive leads has a hole circumscribed by the substrate in which is positioned a die having pads that are bonded to ends of leads carried by the substrate and projecting into the hole for contact with the die pads. The leads include free outer ends that project laterally outwardly and downwardly away from the plane of the substrate for connection to contact pads on a circuit board. The free leads are isolated from pressure applied to the chip on tape assembly after it has been connected to a circuit board by means of a thin self-supporting thermally conductive heat spreader that contacts the side of the die opposite its pads and includes fixed standoff and/or alignment pins that extend through alignment holes in the thin substrate and are in physical contact with a surf ace of the printed circuit board.Type: GrantFiled: September 19, 1996Date of Patent: April 27, 1999Assignee: LSI Logic CorporationInventors: Emily Hawthorne, John McCormick
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Patent number: 5854085Abstract: Separate and distinct conductive layers for power and ground are insulated from one another and a patterned signal conductive layer to form a flexible substrate for mounting a semiconductor die in a semiconductor device assembly. TAB technology is utilized to produce an assembly that has superior electrical characteristics because power and ground is conducted on separate low impedance conductive layers. The power and ground leads connecting the semiconductor die and external circuits are selected from the signal trace layer, cut bent downward and attached by bonding to the respective power or ground layer. A tool is disclosed for cutting the selected leads. A method of attaching solder balls to a TBGA film using solder flux and photoimageable solder resist definition is also disclosed.Type: GrantFiled: April 24, 1996Date of Patent: December 29, 1998Assignee: LSI Logic CorporationInventors: Kurt Raymond Raab, John McCormick
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Patent number: 5831836Abstract: An integrated circuit device package of this invention includes a flexible substrate having an upper patterned insulative layer, and a lower patterned conductive layer including a plurality of package leads. An integrated circuit die is fixed within a void of the upper surface of the flexible substrate. Electrical connections between the integrated circuit die and the package leads are provided. A rigid upper protective layer is present. The rigid upper protective layer encloses the integrated circuit die, and at least partially covers the top surface of the upper insulative layer. The semiconductor device package further comprises a rigid or semi-rigid metal lower protective layer opposite the upper protective layer including a ground plane proximal to the electrical leads and a power plane distal to the leads. Methods of production are also given.Type: GrantFiled: January 30, 1992Date of Patent: November 3, 1998Assignee: LSI LogicInventors: Jon Long, John McCormick
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Patent number: 5801432Abstract: Electronic systems using separate and distinct conductive layers for power and ground are insulated from one another and a patterned signal conductive layer to form a flexible substrate for mounting a semiconductor die in a semiconductor device assembly of the system. TAB technology is utilized to produce an assembly that has superior electrical characteristics because power and ground is conducted on separate low impedance conductive layers. The power and ground leads connecting the semiconductor die and external circuits are selected from the signal trace layer, cut bent downward and attached by bonding to the respective power or ground layer. A tool is disclosed for cutting the selected leads. The present invention further provides a system utilizing a wafer probe card which includes a multi-layer, relatively flexible tape-like substrate having a first conductive layer patterned to have a number of probe leads thereon.Type: GrantFiled: April 16, 1996Date of Patent: September 1, 1998Assignee: LSI Logic CorporationInventors: Michael D. Rostoker, Kurt Raymond Raab, John McCormick
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Patent number: 5786910Abstract: Security devices which are difficult to reproduce include a grid screen metallization pattern. The grid screen metallization pattern may be laid down over a hologram or diffraction grating formed as a surface relief pattern on a substrate, to form a visually identifiable, semi-transparent security device. Additionally, the metallization pattern may include resonant structures in which information about the security device is encoded. In some embodiments of these security devices, the metallization pattern is disposed in accurate registration with the underlying hologram or diffraction grating. These security devices are made by methods which include printing an oil pattern on the substrate. Areas on which oil is deposited do not receive metal during a metallization step. Since these methods do not use caustics, metallization patterns including features which would otherwise trap and hold caustics are possible.Type: GrantFiled: May 11, 1995Date of Patent: July 28, 1998Assignee: Advanced Deposition Technologies, Inc.Inventors: Glenn J. Walters, John A. McCormick
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Patent number: 5763952Abstract: One or two, or more, additional conductive layers, separated from one another (if two or more) and separated from a patterned (signal) conductive layer are formed in a flexible substrate, for mounting a semiconductor die in a semiconductor device assembly. These additional layers are used as separate planes for carrying power and/or ground from outside the assembly to the die, on a separate plane from signals entering or exiting the die. TAB processes are disclosed for cutting, bending and bonding inner and outer portions of selected signal layer traces to respective inner and outer edge portions of the additional conductive layer(s), including a two-stage process of (1) first cutting, bending and tacking the selected traces to the additional layer(s), and then (2) repositioning a bonding tool and securely bonding the selected traces to the additional layer(s). A tool (die pedestal) for aiding in the assembly process is also disclosed.Type: GrantFiled: March 8, 1996Date of Patent: June 9, 1998Assignee: LSI Logic CorporationInventors: Brian Lynch, John McCormick
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Patent number: 5757521Abstract: Security devices which are difficult to reproduce include a grid screen metallization pattern. The grid screen metallization pattern may be laid down over a hologram or diffraction grating formed as a surface relief pattern on a substrate, to form a visually identifiable, semi-transparent security device. Additionally, the metallization pattern may include resonant structures in which information about the security device is encoded. In some embodiments of these security devices, the metallization pattern is disposed in accurate registration with the underlying hologram or diffraction grating. These security devices are made by methods which include printing an oil pattern on the substrate. Areas on which oil is deposited do not receive metal during a metallization step. Since these methods do not use caustics, metallization patterns including features which would otherwise trap and hold caustics are possible.Type: GrantFiled: November 21, 1995Date of Patent: May 26, 1998Assignee: Advanced Deposition Technologies, Inc.Inventors: Glenn J. Walters, Richard C. Shea, John A. McCormick
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Patent number: 5748005Abstract: A radial position sensor includes four capacitive electrodes oriented about a shaft, arranged in two diametrically opposite pairs. Sensor circuitry generates an output signal in proportion to the capacitance between the electrodes and the shaft; the capacitance between an electrode and the shaft increases as the shaft approaches the electrode and decreases as the shaft recedes from the electrode. The sensor circuitry applies an alternating voltage to one electrode of a pair and a 180 degree out of phase alternating voltage to the other electrode of the pair. The electrical responses of the two electrodes to their respective input signals are summed to form a radial deviation signal which is relatively free from the alternating voltage and accurately represents the position of the shaft relative to the electrodes of the pair.Type: GrantFiled: October 31, 1995Date of Patent: May 5, 1998Assignee: Creare, Inc.Inventors: John A. McCormick, Herbert Sixsmith
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Patent number: 5681777Abstract: One or two, or more, additional conductive layers, separated from one another (if two or more) and separated from a patterned (signal) conductive layer are formed in a flexible substrate, for mounting a semiconductor die in a semiconductor device assembly. These additional layers are used as separate planes for carrying power and/or ground from outside the assembly to the die, on a separate plane from signals entering or exiting the die. TAB processes are disclosed for cutting, bending and bonding inner and outer portions of selected signal layer traces to respective inner and outer edge portions of the additional conductive layer(s), including a two-stage process of (1) first cutting, bending and tacking the selected traces to the additional layer(s), and then (2) repositioning a bonding tool and securely bonding the selected traces to the additional layer(s). A tool (die pedestal) for aiding in the assembly process is also disclosed.Type: GrantFiled: March 29, 1996Date of Patent: October 28, 1997Assignee: LSI Logic CorporationInventors: Brian Lynch, John McCormick
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Patent number: 5638596Abstract: One or two, or more, additional conductive layers, separated from one another (if two or more) and separated from a patterned (signal) conductive layer are formed in a flexible substrate, for mounting a semiconductor die in a semiconductor device assembly. These additional layers are used as separate planes for carrying power and/or ground from outside the assembly to the die, on a separate plane from signals entering or exiting the die. Another aspect of the present invention provides a semiconductor device assembly including a first conductive layer with a plurality of traces formed on an insulating layer, a second conductive layer with an inner edge portion exposed within the central opening in the insulating layer, and a leadframe having a number of leads the inner end of one or more of the leads being electrically connected to an outer end of one or more of the traces.Type: GrantFiled: June 5, 1995Date of Patent: June 17, 1997Assignee: LSI Logic CorporationInventor: John McCormick
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Patent number: 5639385Abstract: One or two, or more, additional conductive layers, separated from one another (if two or more) and separated from a patterned (signal) conductive layer are formed in a flexible substrate, for mounting a semiconductor die in a semiconductor device assembly. These additional layers are used as separate planes for carrying power and/or ground from outside the assembly to the die, on a separate plane from signals entering or exiting the die. TAB processes are disclosed for cutting, bending and bonding inner and outer portions of selected signal layer traces to respective inner and outer edge portions of the additional conductive layer(s), including a two-stage process of (1) first cutting, bending and tacking the selected traces to the additional layer(s), and then (2) repositioning a bonding tool and securely bonding the selected traces to the additional layer(s). A tool (die pedestal) for aiding in the assembly process is also disclosed.Type: GrantFiled: June 6, 1995Date of Patent: June 17, 1997Assignee: LSI Logic CorporationInventor: John McCormick
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Patent number: 5552631Abstract: One or two, or more, additional conductive layers, separated from one another (if two or more) and separated from a patterned (signal) conductive layer are formed in a flexible substrate, for mounting a semiconductor die in a semiconductor device assembly. These additional layers are used as separate planes for carrying power and/or ground from outside the assembly to the die, on a separate plane from signals entering or exiting the die. Another aspect of the present invention provides a semiconductor device assembly including a first conductive layer with a plurality of traces formed on an insulating layer, a second conductive layer with an inner edge portion exposed within the central opening in the insulating layer, and a leadframe having a number of leads the inner end of one or more of the leads being electrically connected to an outer end of one or more of the traces.Type: GrantFiled: December 20, 1993Date of Patent: September 3, 1996Assignee: LSI Logic CorporationInventor: John McCormick
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Patent number: 5550406Abstract: One or two, or more, additional conductive layers, separated from one another (if two or more) and separated from a patterned (signal) conductive layer are formed in a flexible substrate, for mounting a semiconductor die in a semiconductor device assembly. These additional layers are used as separate planes for carrying power and/or ground from outside the assembly to the die, on a separate plane from signals entering or exiting the die. TAB processes are disclosed for cutting, bending and bonding inner and outer portions of selected signal layer traces to respective inner and outer edge portions of the additional conductive layer(s), including a two-stage process of (1) first cutting, bending and tacking the selected traces to the additional layer(s), and then (2) repositioning a bonding tool and securely bonding the selected traces to the additional layer(s). A tool (die pedestal) for aiding in the assembly process is also disclosed.Type: GrantFiled: December 20, 1993Date of Patent: August 27, 1996Assignee: LSI Logic CorporationInventor: John McCormick
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Patent number: 5530231Abstract: A conductive structure for use in microwave food packaging which adapts itself to heat food articles in a safer, more uniform manner is disclosed. The structure includes a conductive layer disposed on a non-conductive substrate. Provision in the structure's conductive layer of fuse links and base areas causes microwave induced currents to be channeled through the fuse links, resulting in a controlled heating. When over-exposed to microwave energy, fuses break more readily than the conductive base areas resulting in less absorption of microwave energy in the area of fuse breaks than in other regions where fuses do not break. The arrangement and dimensions of fuse links compensate for known uneven stresses in the substrate, giving uniform fuse performance. In addition, by varying the dimensions of the fuse links and base areas it is possible to design and fabricate different fused microwave conductive structures having a wide range of heating characteristics.Type: GrantFiled: May 1, 1995Date of Patent: June 25, 1996Assignee: Advanced Deposition Technologies, Inc.Inventors: Glenn J. Walters, John A. McCormick
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Patent number: 5489766Abstract: A bag for heating food products in a microwave oven and a blank for forming the bag are disclosed. The bag is formed of a dielectric substrate having a laminated layer including at least one microwave interactive patch. The microwave interactive patches are positioned to avoid overheating at creases and seams formed in the bag. At least one of the microwave interactive patches includes a heat sensitive fuse.Type: GrantFiled: October 24, 1994Date of Patent: February 6, 1996Assignee: Advanced Deposition Technologies, Inc.Inventors: Glenn J. Walters, John A. McCormick
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Patent number: 5412187Abstract: A conductive structure for use in microwave food packaging which adapts itself to heat food articles in a safer, more uniform manner is disclosed. The structure includes a conductive layer disposed on a non-conductive substrate. Provision in the structure's conductive layer of fuse links and base areas causes microwave induced currents to be channeled through the fuse links, resulting in a controlled heating. When over-exposed to microwave energy, fuses break more readily than the conductive base areas resulting in less absorption of microwave energy in the area of fuse breaks than in other regions where fuses do not break. In this way the fused microwave conductive structure compensates for the uneven microwave field within a microwave oven and at the same time provides a safer conductive structure less likely to overheat.Type: GrantFiled: January 25, 1994Date of Patent: May 2, 1995Assignee: Advanced Deposition Technologies, Inc.Inventors: Glenn J. Walters, John A. McCormick
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Patent number: 5410451Abstract: A thin dielectric substrate bearing a plurality of conductive leads has a hole circumscribed by the substrate in which is positioned a die having pads that are bonded to ends of leads carried by the substrate and projecting into the hole for contact with the die pads. The leads include free outer ends that project laterally outwardly and downwardly away from the plane of the substrate for connection to contact pads on a circuit board. The free leads are isolated from pressure applied to the chip on tape assembly after it has been connected to a circuit board by means of a thin self-supporting thermally conductive heat spreader that contacts the side of the die opposite its pads and includes fixed standoff and/or alignment pins that extend through alignment holes in the thin substrate and are in physical contact with a surface of the printed circuit board.Type: GrantFiled: December 20, 1993Date of Patent: April 25, 1995Assignee: LSI Logic CorporationInventors: Emily Hawthorne, John McCormick