Patents by Inventor John O. Jacobson

John O. Jacobson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6064216
    Abstract: A method, apparatus and system for testing semiconductor wafers are provided. The method includes providing a wafer carrier to provide an electrical path for receiving and transmitting test signals to the wafer. The wafer carrier includes a base for retaining the wafer, and an interconnect having contact members configured to establish electrical communication with contact locations on the wafer. The wafer carrier can include one or more compressible spring members configured to bias the wafer and interconnect together in the assembled carrier. The wafer carrier can be assembled, with the wafer in alignment with the interconnect, using optical alignment techniques, and an assembly tool similar to aligner bonder tools used for flip chip bonding semiconductor dice. A system for use with the carrier can include a testing apparatus configured to apply test signals through the carrier to the wafer while the wafer is subjected to temperature cycling.
    Type: Grant
    Filed: February 1, 1999
    Date of Patent: May 16, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Salman Akram, Alan G. Wood, David R. Hembree, James M. Wark, John O. Jacobson
  • Patent number: 6064194
    Abstract: An apparatus for automatically positioning electronic dice within temporary packages to enable continuity testing between the dice bond pads and the temporary package electrical interconnects is provided. The apparatus includes a robot having a programmable robot arm with a gripper assembly, die and lid feeder stations, a die inverter, and a plurality of cameras. The cameras take several pictures of the die and temporary packages to precisely align the die bond pads with the temporary package electrical interconnects. A predetermined assembly position is located along a conveyor that conveys a carrier between a first position, corresponding to an inlet, and a second position, corresponding to an outlet. The die, a restraining device and temporary package are assembled at the predetermined assembly position and tested for continuity therebetween. The apparatus further includes a fifth camera which locates the die at a wafer handler.
    Type: Grant
    Filed: December 17, 1996
    Date of Patent: May 16, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Jennifer L. Folaron, Robert J. Folaron, David R. Hembree, John O. Jacobson, Jay C. Nelson, Lelan D. Warren
  • Patent number: 6057597
    Abstract: A semiconductor package includes a substrate having one or more dice mounted thereto, and a cover adapted to protect and form a sealed space for the dice. The cover can be pre-fabricated of molded plastic, or stamped metal, and attached to the substrate using a cured seal. A hole can also be provided through the substrate to permit pressure equalization during formation of the seal. The cover can be prefabricated in an enclosed configuration for attachment directly to the substrate, or in a planar configuration for attachment to a peripheral ridge on the substrate. In either embodiment, the cover is removable to permit defective dice to be replaced or repaired.
    Type: Grant
    Filed: October 14, 1998
    Date of Patent: May 2, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, David R. Hembree, Derek Gochnour, Salman Akram, John O. Jacobson, James M. Wark, Steven G. Thummel
  • Patent number: 6045026
    Abstract: A machine and method for bonding puncture-type conductive contact members of an interconnect to the bond pads of a bare semiconductor die includes the use of one or two ultrasonic vibrators mounted to vibrate one or both of the die and interconnect. A short axial linear burst of ultrasonic energy enables the contact members to pierce hard oxide layers on the surfaces of the bond pads at a much lower compressive force and rapidly achieve full penetration depth.
    Type: Grant
    Filed: February 23, 1998
    Date of Patent: April 4, 2000
    Assignee: Micron Technology, Inc.
    Inventors: David R. Hembree, Michael E. Hess, John O. Jacobson, Warren M. Farnworth, Alan G. Wood
  • Patent number: 6009025
    Abstract: The partial replacement of partially defective integrated circuit devices, such as memory devices, is disclosed. In one embodiment, the data lines coupled to different sections of the memory array of a memory device have inserted in series therein normally closed links. If a section is found to be defective, then the link for the data line coupled to the section is opened. This permits a repair device to be coupled to the memory device such that only the defective section is replaced. The address and control lines of the repair device are coupled to their counterpart lines of the memory device. However, a data line of the repair device is coupled to a data line of the memory device only if the data line of the memory device is coupled to a defective section.
    Type: Grant
    Filed: June 4, 1999
    Date of Patent: December 28, 1999
    Assignee: Micron Technology, Inc.
    Inventor: John O. Jacobson
  • Patent number: 5955877
    Abstract: A method and apparatus of assembling and disassembling semiconductor dice to be tested from the components of a temporary test package. A computer-controlled vision system is employed to align the dice with the temporary test package bases, and an automated robot arm system is employed to retrieve and assemble the dice with the various package components. The invention has particular utility in the burn-in and other pre-packaging testing of dice to establish known good dice (KGD).
    Type: Grant
    Filed: October 13, 1998
    Date of Patent: September 21, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Alan G. Wood, John O. Jacobson, David R. Hembree, James M. Wark, Jennifer L. Folaron, Robert J. Folaron, Jay C. Nelson, Lelan D. Warren
  • Patent number: 5952840
    Abstract: A method, apparatus and system for testing semiconductor wafers are provided. The method includes providing a wafer carrier to provide an electrical path for receiving and transmitting test signals to the wafer. The wafer carrier includes a base for retaining the wafer, and an interconnect having contact members configured to establish electrical communication with contact locations on the wafer. The wafer carrier can include one or more compressible spring members configured to bias the wafer and interconnect together in the assembled carrier. The wafer carrier can be assembled, with the wafer in alignment with the interconnect, using optical alignment techniques, and an assembly tool similar to aligner bonder tools used for flip chip bonding semiconductor dice. A system for use with the carrier can include a testing apparatus configured to apply test signals through the carrier to the wafer while the wafer is subjected to temperature cycling.
    Type: Grant
    Filed: December 31, 1996
    Date of Patent: September 14, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Salman Akram, Alan G. Wood, David R. Hembree, James M. Wark, John O. Jacobson
  • Patent number: 5931685
    Abstract: An interconnect and system for establishing temporary electrical communication with semiconductor components having contact bumps are provided. The interconnect includes a substrate with patterns of contact members adapted to electrically contact the contact bumps. The substrate can be formed of a material such as ceramic, silicon, FR-4, or photo-chemically machineable glass. The contact members can be formed as recesses covered with conductive layers in electrical communication with conductors and terminal contacts on the substrate. Alternately, the contact members can be formed as projections adapted to penetrate the contact bumps, as microbumps with a rough textured surface, or as a deposited layer formed with recesses. The interconnect can be employed in a wafer level test system for testing dice contained on a wafer, or in a die level test system for testing bare bumped dice or bumped chip scale packages.
    Type: Grant
    Filed: June 2, 1997
    Date of Patent: August 3, 1999
    Assignee: Micron Technology, Inc.
    Inventors: David R. Hembree, John O. Jacobson, James M. Wark, Warren M. Farnworth, Salman Akram, Alan G. Wood
  • Patent number: 5920513
    Abstract: The partial replacement of partially defective integrated circuit devices, such as memory devices, is disclosed. In one embodiment, the data lines coupled to different sections of the memory array of a memory device have inserted in series therein normally closed links. If a section is found to be defective, then the link for the data line coupled to the section is opened. This permits a repair device to be coupled to the memory device such that only the defective section is replaced. The address and control lines of the repair device are coupled to their counterpart lines of the memory device. However, a data line of the repair device is coupled to a data line of the memory device only if the data line of the memory device is coupled to a defective section.
    Type: Grant
    Filed: August 22, 1997
    Date of Patent: July 6, 1999
    Assignee: Micron Technology, Inc.
    Inventor: John O. Jacobson
  • Patent number: 5915977
    Abstract: An interconnect and system for establishing temporary electrical communication with semiconductor components having contact bumps are provided. The interconnect includes a substrate with patterns of contact members adapted to electrically contact the contact bumps. The substrate can be formed of a material such as ceramic, silicon, FR-4, or photo-chemically machineable glass. The contact members can be formed as recesses covered with conductive layers in electrical communication with conductors and terminal contacts on the substrate. Alternately, the contact members can be formed as projections adapted to penetrate the contact bumps, as microbumps with a rough textured surface, or as a deposited layer formed with recesses. The interconnect can be employed in a wafer level test system for testing dice contained on a wafer, or in a die level test system for testing bare bumped dice or bumped chip scale packages.
    Type: Grant
    Filed: August 24, 1998
    Date of Patent: June 29, 1999
    Assignee: Micron Technology, Inc.
    Inventors: David R. Hembree, John O. Jacobson, James M. Wark, Warren M. Farnworth, Salman Akram, Alan G. Wood
  • Patent number: 5907492
    Abstract: An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on IC's at probe to determine whether any further repairs will be conducted later in the manufacturing process includes storing the data in association with a fuse ID of each of the IC's. The ID codes of the IC's are automatically read, for example, at an opens/shorts test during the manufacturing process. The data stored in association with the ID codes of the IC's is then accessed, and additional repair procedures the IC's may undergo are selected in accordance with the accessed data. Thus, for example, the accessed data may indicate that an IC is unrepairable, so the IC can proceed directly to a scrap bin without having to be queried to determine whether it is repairable, as is necessary in traditional IC manufacturing processes.
    Type: Grant
    Filed: June 6, 1997
    Date of Patent: May 25, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Warren M. Farnworth, Derek J. Gochnour, David R. Hembree, Michael E. Hess, John O. Jacobson, James M. Wark, Alan G. Wood
  • Patent number: 5895222
    Abstract: An electronic device includes at least one chip connected to a circuit board. The chip includes a die and an encapsulant which is applied in a liquid phase and dries to a solid phase. A shell may be positioned over the chip and in some embodiments of the invention extends over the entire device. A dam is connected to the circuit board adjacent the die in at least one direction so as to restrain flow of the encapsulant toward the dam when the encapsulant is in the liquid phase. The dam may include an upper end at an elevation higher than the uppermost portion of the chip (which would usually be encapsulated), the dam acting as a standoff between the shell and the chip. The upper end of the dam may be constantly in contact with the shell or, alternatively, the upper end of the dam may be ordinarily not in contact with the shell, but comes into contact with the shell if the shell is compressed or flexed toward the chip. A single dam may surround the die (and chip structure after the encapsulant dries).
    Type: Grant
    Filed: July 10, 1997
    Date of Patent: April 20, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Walter L. Moden, John O. Jacobson
  • Patent number: 5893726
    Abstract: A semiconductor package includes a substrate having one or more dice mounted thereto, and a cover adapted to protect and form a sealed space for the dice. The cover can be pre-fabricated of molded plastic, or stamped metal, and attached to the substrate using a cured seal. A hole can also be provided through the substrate to permit pressure equalization during formation of the seal. The cover can be prefabricated in an enclosed configuration for attachment directly to the substrate, or in a planar configuration for attachment to a peripheral ridge on the substrate. In either embodiment, the cover is removable to permit defective dice to be replaced or repaired.
    Type: Grant
    Filed: December 15, 1997
    Date of Patent: April 13, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, David R. Hembree, Derek Gochnour, Salman Akram, John O. Jacobson, James M. Wark, Steven G. Thummel
  • Patent number: 5894167
    Abstract: An electronic device includes at least one chip connected to a circuit board. The chip includes a die and an encapsulant which is applied in a liquid phase and dries to a solid phase. A shell may be positioned over the chip and in some embodiments of the invention extends over the entire device. A dam is connected to the circuit board adjacent the die in at least one direction so as to restrain flow of the encapsulant toward the dam when the encapsulant is in the liquid phase. The dam may include an upper end at an elevation higher than the uppermost portion of the chip (which would usually be encapsulated), the dam acting as a standoff between the shell and the chip. The upper end of the dam may be constantly in contact with the shell or, alternatively, the upper end of the dam may be ordinarily not in contact with the shell, but comes into contact with the shell if the shell is compressed or flexed toward the chip. A single dam may surround the die (and chip structure after the encapsulant dries).
    Type: Grant
    Filed: May 8, 1996
    Date of Patent: April 13, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Walter L. Moden, John O. Jacobson
  • Patent number: 5894218
    Abstract: A method and apparatus of assembling and disassembling semiconductor dice to be tested from the components of a temporary test package. A computer-controlled vision system is employed to align the dice with the temporary test package bases, and an automated robot arm system is employed to retrieve and assemble the dice with the various package components. The invention has particular utility in the burn-in and other pre-packaging testing of die to establish known good dice (KGD).
    Type: Grant
    Filed: August 7, 1996
    Date of Patent: April 13, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Alan G. Wood, John O. Jacobson, David R. Hembree, James M. Wark, Jennifer L. Folaron, Robert J. Folaron, Jay C. Nelson, Lelan D. Warren
  • Patent number: 5786632
    Abstract: A method for packaging a semiconductor die includes forming an additional protective layer and conductive traces on the die. The die is then placed in a multi-die holder having electrical connectors for establishing an electrical connection to the conductive traces. The protective layer is formed as a thin or thick film of an electrically insulating material such as a polymer, glass, nitride or oxide. In addition, the protective layer can be formed with a tapered peripheral edge to facilitate insertion of the die into the die holder.
    Type: Grant
    Filed: September 24, 1996
    Date of Patent: July 28, 1998
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Alan G. Wood, Trung Tri Doan, John O. Jacobson
  • Patent number: 5593927
    Abstract: A method for packaging a semiconductor die includes forming an additional protective layer and conductive traces on the die. The die is then placed in a multi-die holder having electrical connectors for establishing an electrical connection to the conductive traces. The protective layer is formed as a thin or thick film of an electrically insulating material such as a polymer, glass, nitride or oxide. In addition, the protective layer can be formed with a tapered peripheral edge to facilitate insertion of the die into the die holder.
    Type: Grant
    Filed: December 1, 1995
    Date of Patent: January 14, 1997
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Alan G. Wood, Trung T. Doan, John O. Jacobson