Patents by Inventor John W. Smith

John W. Smith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6202297
    Abstract: A connector for microelectronic devices having bump leads and methods for fabricating and using the connector. A dielectric substrate has a plurality of posts extending upwardly from a front surface. The posts may be arranged in an array of post groups each group defining a gap therebetween. A generally laminar contact extends from each post top. The bump leads are each inserted within a respective gap thereby engaging the contacts which wipe against the bump lead as it continues to be inserted. Typically, distal portions of the contacts deflect downwardly toward the substrate and outwardly away from the center of the gap as the bump lead is inserted into a gap.
    Type: Grant
    Filed: May 14, 1998
    Date of Patent: March 20, 2001
    Assignee: Tessera, Inc.
    Inventors: Anthony B. Faraci, James B. Zaccardi, Thomas H. Distefano, John W. Smith
  • Patent number: 6204091
    Abstract: A method of encapsulating a microelectronic assembly includes providing one or more microelectronic assemblies having one or more elements defining exterior surfaces and an array of terminals exposed at the exterior surfaces, the one or more elements defining one or more apertures through the exterior surfaces. A layer of a curable barrier material is then provided on a supporting element. The barrier layer has openings therein in a pattern corresponding to the array of terminals on the one or more microelectronic assemblies. The supporting element and the one or more microelectronic elements are then assembled together so that the layer of barrier material contacts the exterior surfaces and covers the apertures and so that the openings in the layer of barrier material are aligned with the terminals. The barrier material is then cured while in contact with the exterior surfaces to thereby form a barrier layer covering the apertures.
    Type: Grant
    Filed: February 17, 2000
    Date of Patent: March 20, 2001
    Assignee: Tessera, Inc.
    Inventors: John W. Smith, Joseph Fjelstad
  • Patent number: 6202298
    Abstract: A method of making a microelectronic assembly includes providing a first microelectronic element and a second microelectronic element with confronting, spaced-apart surfaces defining a space therebetween and providing one or more masses of a fusible conductive material having a melting temperature below about 150° C. in said space, whereby the fusible conductive masses connect the first and second microelectronic elements to one another. Next, a flowable material is introduced between the confronting surfaces of the first and second microelectronic elements and around the one or more fusible conductive masses and the flowable material is then cured to provide a compliant layer disposed between said confronting surfaces and intimately surrounding each fusible conductive mass. The fusible conductive masses are capable of electrically interconnecting the contacts on microelectronic elements confronting one another and/or conducting heat between confronting microelectronic elements.
    Type: Grant
    Filed: November 3, 1997
    Date of Patent: March 20, 2001
    Assignee: Tessera, Inc.
    Inventor: John W. Smith
  • Publication number: 20010000032
    Abstract: A method of making a microelectronic assembly includes bonding a plurality of lead connection sections arranged in a row to contacts of a microelectronic element such as a semiconductor chip having contacts in rows at the periphery of the chip. The leads have terminal sections secured to a dielectric support structure, and horizontally curved sections between the terminal regions and bond regions. After bonding, the dielectric support structure is lifted upwardly relative to the chip, so as to bend the leads into a vertically-extensive orientation. Partial straightening of the original horizontal curvature allows each lead to stretch and accommodate the vertical movement.
    Type: Application
    Filed: November 30, 2000
    Publication date: March 15, 2001
    Inventors: John W. Smith, Thomas H. Distefano
  • Patent number: 6194291
    Abstract: A microelectronic connection component includes a support such as a dielectric sheet having elongated leads extending along a surface. The leads have terminal ends permanently connected to the support and tip ends releasably connected to the support. The support is juxtaposed with a further element such as a semiconductor chip or wafer, and tip ends of the leads are bonded to contacts on the wafer using a bonding tool advanced through holes in the support. After bonding, the support and the further element are moved away from one another so as to deform the leads.
    Type: Grant
    Filed: August 9, 1999
    Date of Patent: February 27, 2001
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, John W. Smith
  • Patent number: 6191368
    Abstract: A lead element for a microelectronic connection has a rigid body section connected to two parallel strip-like flexible leg sections. The leg sections each have tip ends that are offset from the rigid body section in a horizontal direction. The tip end of one leg section is permanently connected to a first microelectronic element. The tip end of the other leg section is releasably connected to the first microelectronic element and permanently connected to a second microelectronic element. Moving the first tip end relative to the second tip end in a vertical direction causes flexure of the leg sections in opposite directions.
    Type: Grant
    Filed: September 12, 1996
    Date of Patent: February 20, 2001
    Assignee: Tessera, Inc.
    Inventors: Thomas Di Stefano, John W. Smith
  • Patent number: 6147400
    Abstract: A plurality of separate semiconductor chips, each having a contact-bearing surface and contacts on such surface, are disposed in an array so that the contact-bearing surfaces face and define a first surface of the array. A flexible, dielectric sheet with terminals thereon overlies the first or contact bearing surface of the semiconductor chips. Elongated leads are disposed between the dielectric element and the semiconductor chips. Each lead has a first end connected to a terminal on the dielectric element, and a second end connected to a contact on a semiconductor chip in the array. All of the leads are formed simultaneously by moving the dielectric element and the array relative to one another to simultaneously displace all of the first ends of the leads relative to all of the second ends. The dielectric element is subdivided after the forming step so as to leave one region of the dielectric element connected to each chip and thereby form individual units each including one chip, or a small number of chips.
    Type: Grant
    Filed: June 10, 1998
    Date of Patent: November 14, 2000
    Assignee: Tessera, Inc.
    Inventors: Tony Faraci, Thomas H. DiStefano, John W. Smith
  • Patent number: 6133639
    Abstract: A method and an apparatus for providing a planar and compliant interface between a semiconductor chip and its supporting substrate to accommodate for the thermal coefficient of expansion mismatch therebetween. The complaint interface is comprised of a plurality of compliant pads defining channels between adjacent pads. The pads are typically compressed between a flexible film chip carrier and the chip. A compliant filler is further disposed within the channels to form a uniform encapsulation layer having a controlled thickness.
    Type: Grant
    Filed: April 24, 1997
    Date of Patent: October 17, 2000
    Assignee: Tessera, Inc.
    Inventors: Zlata Kovac, Craig Mitchell, Thomas H. Distefano, John W. Smith
  • Patent number: 6130116
    Abstract: A method of encapsulating a microelectronic assembly includes providing one or more microelectronic assemblies having one or more elements defining exterior surfaces and an array of terminals exposed at the exterior surfaces, the one or more elements defining one or more apertures through the exterior surfaces. A layer of a curable barrier material is then provided on a supporting element. The barrier layer has openings therein in a pattern corresponding to the array of terminals on the one or more microelectronic assemblies. The supporting element and the one or more microelectronic elements are then assembled together so that the layer of barrier material contacts the exterior surfaces and covers the apertures and so that the openings in the layer of barrier material are aligned with the terminals. The barrier material is then cured while in contact with the exterior surfaces to thereby form a barrier layer covering the apertures.
    Type: Grant
    Filed: December 4, 1997
    Date of Patent: October 10, 2000
    Assignee: Tessera, Inc.
    Inventors: John W. Smith, Joseph Fjelstad
  • Patent number: 6117694
    Abstract: A microelectronic component, such as a connector or a packaged semiconductor device is made by connecting multiple leads between a pair of elements and moving the elements away from one another so as to bend the leads toward a vertically extensive disposition. One of the elements includes a temporary support which is removed after the bending operation and after injecting and curing a dielectric material to form a dielectric layer surrounding and supporting the leads.
    Type: Grant
    Filed: March 12, 1999
    Date of Patent: September 12, 2000
    Assignee: Tessera, Inc.
    Inventors: John W. Smith, Belgacem Haba
  • Patent number: 6114763
    Abstract: An electronic assembly which includes a semiconductor chip package having an array of package terminals and a translator. The translator has a first array of terminals exposed on a first surface of the translator and a second array of terminals exposed on a second surface of the translator. The pitch of the first array matches the pitch of the semiconductor package. The pitch of the second array matches the pitch of the printed circuit board to which the electronic assembly is to be mounted. The array of package terminals on the semiconductor chip package is aligned with and bonded to the first array of terminals on the translator to form the electronic assembly. The electronic assembly can then be mounted on a board by aligning and bonding the second array of terminals on the translator with the connection pads on the printed circuit board.
    Type: Grant
    Filed: May 29, 1998
    Date of Patent: September 5, 2000
    Assignee: Tessera, Inc.
    Inventor: John W. Smith
  • Patent number: 6104087
    Abstract: A microelectronic connection component includes a dielectric sheet having an area array of elongated, strip-like leads. Each lead has a terminal end fastened to the sheet and a tip end detachable from the sheet. Each lead extends horizontally parallel to the sheet, from its terminal end to its tip end. The tip ends are attached to a second element, such as another dielectric sheet or a semiconductor wafer. The first and second elements are then moved relative to one another to advance the tip end of each lead vertically away from the dielectric sheet and deform the leads into a bent, vertically extensive configuration. The preferred structures provide semiconductor chip assemblies with a planar area array of contacts on the chip, an array of terminals on the sheet positioned so that each terminal is substantially over the corresponding contact, and an array of metal S-shaped ribbons connected between the terminals and contacts.
    Type: Grant
    Filed: August 24, 1998
    Date of Patent: August 15, 2000
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, John W. Smith
  • Patent number: 6096574
    Abstract: A method of making a microelectronic assembly includes providing a first element and a second element with confronting, spaced-apart interior surfaces defining a space therebetween and contacts on the interior surfaces and masses of an electrically conductive material having a melting temperature below about 125.degree. C. in the space so that each mass is disposed between a contact on the first element and a contact on the second element and so that the masses electrically connect the contacts to one another. A flowable liquid material is then introduced around the masses and between the confronting surfaces, and the liquid material is then cured to form a compliant dielectric layer disposed between the confronting surfaces and intimately surrounding each mass.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: August 1, 2000
    Assignee: Tessera, Inc.
    Inventor: John W. Smith
  • Patent number: 6080603
    Abstract: In a method for mounting a sheet-like microelectronic element, the sheet-like element comprises a dielectric layer having a top surface and a bottom surface and is first bonded to an expansion ring. The expansion ring is then heated to stretch the sheet-like element. A frame ring, having an external diameter smaller than the internal diameter of the expansion ring, is then bonded to the sheet-like element. A plurality of leads are formed on the bottom surface of the sheet-like element, the leads including bonding pads. In other embodiments, a method is provided for bonding bond pads on a sheet-like microelectronic element to contacts on a microelectronic component.
    Type: Grant
    Filed: March 15, 1999
    Date of Patent: June 27, 2000
    Assignee: Tessera, Inc.
    Inventors: Thomas Distefano, John W. Smith, Anthony B. Faraci
  • Patent number: 6080932
    Abstract: A semiconductor chip package includes a semiconductor chip having surfaces and contacts, a layer of a moisture-permeable material bonded to one surface of the chip and a moisture-impermeable encapsulant overlying the moisture-permeable material and at least partially surrounding the chip. The package has exposed exterior surfaces and terminals on at least one of the exposed exterior surfaces which are electrically connected to the contacts. The moisture-permeable material extends to at least one of the exposed exterior surfaces so that moisture may be vented through the moisture-permeable material and out of the package. In certain embodiments, the moisture-permeable material includes a compliant layer having silicone and the moisture-impermeable material includes an epoxy.
    Type: Grant
    Filed: April 14, 1998
    Date of Patent: June 27, 2000
    Assignee: Tessera, Inc.
    Inventors: John W. Smith, Christopher M. Pickett
  • Patent number: 6048175
    Abstract: A system for controlling one or more borehole pumps to enable pumping-on-demand is described. The system uses a computerized controller which, in combination with sensors, monitors and controls the activity of the pump, thereby controlling fluid in the borehole. The system is continually in one of three modes, the monitoring mode, the pump mode, and the recovery mode. Within each cycle of modes, the system performs multiple checks on the apparatus involved. The data obtained during the check is stored in appropriate databases as well as checked against predetermined norms. In the event of a malfunction within the apparatus, or other supervised and/or monitored functions, the system can activate a notification system, such as a centralized monitoring facility. A pump is disclosed with a fluid sensor to detect the presence of fluid and transmit this presence to the computerized monitoring system. A slug sensor notifies the computer of the beginning and end of a predetermined quantity of fluid.
    Type: Grant
    Filed: September 24, 1998
    Date of Patent: April 11, 2000
    Inventors: Edward A. Corlew, Henry B. Steen, III, John W. Smith
  • Patent number: 6044548
    Abstract: A method of making connections to a microelectronic unit includes the steps of providing a connection component having a flexible dielectric top sheet, a plurality of terminals on the top sheet and a plurality of electrically conductive, elongated flexible leads connected to the terminals and extending side-by-side downwardly from the terminals away from the top sheet to bottom ends remote from the top sheet. The connection component is then engaged with a front surface of a microelectronic unit having an array of contacts thereon while subjecting the connection component and the microelectronic unit to heat and pressure so that bottom ends of the leads remote from the top sheet bond with the contacts on the microelectronic unit to form electrical connections therewith.
    Type: Grant
    Filed: March 10, 1998
    Date of Patent: April 4, 2000
    Assignee: Tessera, Inc.
    Inventors: Thomas H. Distefano, John W. Smith, Jr.
  • Patent number: 6030856
    Abstract: A method of making a microelectronic package includes providing first and second microelectronic elements having electrically conductive parts and disposing a resilient element having one or more intermediary layers capable of being wetted by an adhesive between the microelectronic elements. The resilient element includes fibrous material, a fibrous matrix and/or voids formed at the intermediary layers thereof. An adhesive is provided between the intermediary layers and the microelectronic elements. The adhesive is then cured while it remains in contact with the intermediary layers for bonding the resilient element and the microelectronic elements. The electrically conductive parts are then bonded together to form electrical interconnections. A microelectronic package comprising a resilient element including one or more intermediary layers capable of being wetted by an adhesive is also provided.
    Type: Grant
    Filed: June 10, 1997
    Date of Patent: February 29, 2000
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, Zlata Kovac, John W. Smith
  • Patent number: 6012224
    Abstract: The present invention provides an interconnection scheme having compliant contacts arranged in an array to connect conductive surfaces on a microelectronic device and a supporting substrate, such as a printed circuit board. This invention accommodates for the difference in thermal coefficients of expansion between the device and the supporting substrate. Typically, an area array of conductive contact pads are connected into rows by conductive leads on a flexible, intermediate substrate. Each of the conductive leads bridges a bonding hole in the intermediate substrate which is situated between successive contact pads. Each of the conductive leads further has a frangible portion within or near each bonding hole. A stand-off between the intermediate substrate and the device is create by compliant dielectric pads, typically composed of an elastomer material, positioned under each contact pad.
    Type: Grant
    Filed: September 25, 1997
    Date of Patent: January 11, 2000
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, John W. Smith, Zlata Kovac, Konstantine Karavakis
  • Patent number: 6002168
    Abstract: A microelectronic component for mounting a rigid substrate, such as a hybrid circuit to a rigid support substrate, such as a printed circuit board. The microelectronic component includes a rigid interposer which may have a chip mounted on its first surface; a pattern of contacts on the rigid interposer; a flexible interposer overlying the second surface of the rigid interposer; a pattern of terminals on the flexible interposer; flexible leads; and solder coated copper balls mounted on the flexible interposer. The microelectronic component may have a socket assembly mounted on the first surface of the rigid interposer. The microelectronic component may be mounted on a rigid support substrate.
    Type: Grant
    Filed: November 25, 1997
    Date of Patent: December 14, 1999
    Assignee: Tessera, Inc.
    Inventors: Pieter H. Bellaar, Thomas H. DiStefano, Joseph Fjelstad, Christopher M. Pickett, John W. Smith