Patents by Inventor John W. Smith

John W. Smith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6274820
    Abstract: An interposer for interconnection between microelectronic circuit panels has contacts at its surfaces. Each contact has a central axis normal to the surface and a peripheral portion adapted to expand radially outwardly from the central axis responsive to a force applied by a pad on the engaged circuit panel. Thus, when the circuit panels are compressed with the interposers, the contacts expand radially and wipe across the pads. The wiping action facilitates bonding of the contacts to the pads, as by conductive bonding material carried on the contacts themselves.
    Type: Grant
    Filed: September 1, 2000
    Date of Patent: August 14, 2001
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, John W. Smith, Konstantine N. Karavakis, Zlata Kovac, Joseph Fjelstad
  • Publication number: 20010010400
    Abstract: A sheet such as a polymeric dielectric has elongated lead regions partially separated from the main region of the sheet by gaps in the sheet, and has conductors extending along the lead regions. The lead regions are connected to contacts on a microelectronic element, and the microelectronic element is moved away from the main region of the sheet, thereby bending the lead regions downwardly to form leads projecting from the main region of the sheet.
    Type: Application
    Filed: March 2, 2001
    Publication date: August 2, 2001
    Inventors: John W. Smith, Joseph Fjelstad
  • Patent number: 6266874
    Abstract: A method of making a microelectronic component by providing a conductive element, providing a resist at selected locations on said conductive element and electrophoretically depositing an uncured dielectric material on the conductive element, wherein the uncured material will be deposited on the conductive element except at locations covered by the resist. The deposited material is cured to form a dielectric layer and the resist is removed so that the dielectric layer has openings extending to the conductive element at locations the locations which were covered by the resist.
    Type: Grant
    Filed: July 17, 1998
    Date of Patent: July 31, 2001
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, John W. Smith, Konstantine N. Karavakis, Zlata Kovac, Joseph Fjelstad
  • Patent number: 6265759
    Abstract: A semiconductor chip package having an internal laterally curved lead in order to compensate for the CTE mismatch between a semiconductor chip and a supporting substrate, such as a PWB.
    Type: Grant
    Filed: July 21, 1998
    Date of Patent: July 24, 2001
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, Joseph Fjelstad, John W. Smith
  • Patent number: 6265765
    Abstract: A packaged semiconductor chip including the chip, and a package element such as a heat sink is made by connecting flexible leads between contacts on the chip and terminals on a dielectric element such as a sheet or plate and moving the sheet or plate away from the chip, and injecting a liquid material to form a compliant layer filling the space between the package element and the dielectric element, and surrounding the leads. The dielectric element and package element extend outwardly beyond the edges of the chip, and physically protect the chip. The assembly may be handled and mounted by conventional surface mounting techniques. The assembly may include additional circuit elements such as capacitors used in conjunction with the chip.
    Type: Grant
    Filed: September 23, 1997
    Date of Patent: July 24, 2001
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, John W. Smith, Tony Faraci
  • Patent number: 6255723
    Abstract: A layered lead is disclosed including a layer of structural material which has top and bottom sides, a layer of fatigue-resistant material on the top and bottom surfaces and a layer of bonding material covering the fatigue-resistant layer on the bottom surface for connection to a contact on a chip. An asymmetrical distribution of bonding material on the top and bottom sides may be used to provide reinforcement of the lead against stress. The fatigue-resistant material also acts as a barrier against diffusion between the metal layers.
    Type: Grant
    Filed: October 27, 1998
    Date of Patent: July 3, 2001
    Assignee: Tessera, Inc.
    Inventors: David Light, John W. Smith, Thomas H. DiStefano, David R. Baker, Hung-Ming Wang
  • Publication number: 20010001989
    Abstract: A method of making a microelectronic assembly includes providing a first microelectronic element and a second microelectronic element with confronting, spaced-apart surfaces defining a space therebetween and providing one or more masses of a fusible conductive material having a melting temperature below about 150° C. in said space, whereby the fusible conductive masses connect the first and second microelectronic elements to one another. Next, a flowable material is introduced between the confronting surfaces of the first and second microelectronic elements and around the one or more fusible conductive masses and the flowable material is then cured to provide a compliant layer disposed between said confronting surfaces and intimately surrounding each fusible conductive mass. The fusible conductive masses are capable of electrically interconnecting the contacts on microelectronic elements confronting one another and/or conducting heat between confronting microelectronic elements.
    Type: Application
    Filed: January 10, 2001
    Publication date: May 31, 2001
    Inventor: John W. Smith
  • Patent number: 6239384
    Abstract: A microelectronic connection component has flexible leads formed by polymeric strips with metallic conductors thereon. The metallic conductors may be very thin, desirably less than 5 microns thick, and provide good fatigue resistance. Each strip may have two conductors thereon, one serving as a principal or first signal conductor for connection to a first contact on a chip or other microelectronic element and the other serving as potential reference or ground conductor, or as a second signal conductor connected to a second contact on the chip. The system provides enhanced resistance to crosstalk and rapid signal transmission, and is compatible with differential signal transmission.
    Type: Grant
    Filed: February 9, 1998
    Date of Patent: May 29, 2001
    Assignee: Tessera, Inc.
    Inventors: John W. Smith, Joseph Fjelstad
  • Patent number: 6238938
    Abstract: A method of making a microelectronic assembly includes providing a first element and a second element with confronting, spaced-apart interior surfaces defining a space therebetween and contacts on the interior surfaces and masses of an electrically conductive material having a melting temperature below about 125° C. in the space so that each mass is disposed between a contact on the first element and a contact on the second element and so that the masses electrically connect the contacts to one another. A flowable liquid material is then introduced around the masses and between the confronting surfaces, and the liquid material is then cured to form a compliant dielectric layer disposed between the confronting surfaces and intimately surrounding each mass.
    Type: Grant
    Filed: May 4, 1999
    Date of Patent: May 29, 2001
    Assignee: Tessera, Inc.
    Inventor: John W. Smith
  • Patent number: 6239386
    Abstract: An interposer for interconnection between microelectronic circuit panels has contacts at its surfaces. Each contact has a central axis normal to the surface and a peripheral portion adapted to expand radially outwardly from the central axis responsive to a force applied by a pad on the engaged circuit panel. Thus, when the circuit panels are compressed with the interposers, the contacts expand radially and wipe across the pads. The wiping action facilitates bonding of the contacts to the pads, as by conductive bonding material carried on the contacts themselves.
    Type: Grant
    Filed: August 12, 1996
    Date of Patent: May 29, 2001
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, John W. Smith, Konstantine N. Karavakis, Zlata Kovac, Joseph Fjelstad
  • Patent number: 6232152
    Abstract: A method of manufacturing a plurality of semiconductor chips packages and the resulting chip package assemblies. The method includes providing a circuitized substrate having terminals and leads. A spacer layer is deposited or attached to the substrate and each chip is then attached to the spacer layer. The leads interconnect contacts on the chip to the terminals on the substrate wherein at least some of the terminals lie outside the periphery of the chip. Typically, the spacer layer is comprised of a compliant or resilient material. A curable encapsulant material is deposited so as to encapsulate the leads and at least one surface of the chip. A unitary support structure is then aligned and attached to the encapsulant around the edges of the chips. The encapsulant material is then cured thereby defining a composite of chip assemblies which may be singulated into individual chip packages.
    Type: Grant
    Filed: April 28, 1998
    Date of Patent: May 15, 2001
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, John W. Smith, Craig Mitchell
  • Patent number: 6228685
    Abstract: A microelectronic component is fabricated by bonding a flexible sheet in tension on a rigid frame so that the sheet spans an aperture in the frame, and performing one or more operations on features on the flexible sheet which will be incorporated into the finished component. The fame maintains dimensional stability of the sheet and aids in regsitration of the sheet with external elements such as processing tools or other parts which are to be assembled with the sheet. Desirably, the frame has a coefficient of thermal expansion different from that of the sheet so that when the sheet is brought from the bonding temperature to the temperature used in processing, differential thermal expansion or contraction will cause increased tension in the sheet.
    Type: Grant
    Filed: October 16, 1998
    Date of Patent: May 8, 2001
    Assignee: Tessera, Inc.
    Inventors: Masud Beroz, Thomas H. DiStefano, John W. Smith
  • Patent number: 6228686
    Abstract: A sheet such as a polymeric dielectric has elongated lead regions partially separated from the main region of the sheet by gaps in the sheet, and has conductors extending along the lead regions. The lead regions are connected to contacts on a microelectronic element, and the microelectronic element is moved away from the main region of the sheet, thereby bending the lead regions downwardly to form leads projecting from the main region of the sheet.
    Type: Grant
    Filed: August 26, 1998
    Date of Patent: May 8, 2001
    Assignee: Tessera, Inc.
    Inventors: John W. Smith, Joseph Fjelstad
  • Patent number: 6217972
    Abstract: A flexible sheet used in manufacture of microelectronic components is held on a frame formed from a rigid material so that the frame maintains the sheet under tension during processing and thereby stabilizes the dimensions of the sheet. The frame may be formed from a rigid, light-transmissive material such as a glass, and the bond between the frame and sheet may be made or released by light transmitted through the frame. Preferred features of the framed sheet minimize entrapment of processing liquids such as etch solutions, thereby minimizing carryover of processing solutions between steps. The frame may have contact openings which permit engagement of a metallic layer on the sheet by an electrode carrying electroplating or etching current without disturbing the main portion of the sheet where features are to be formed or treated.
    Type: Grant
    Filed: October 16, 1998
    Date of Patent: April 17, 2001
    Assignee: Tessera, Inc.
    Inventors: Masud Beroz, Thomas H. DiStefano, Matthew T. Hendrickson, David Light, John W. Smith
  • Patent number: 6218213
    Abstract: Flexible leads for making electrical connection in microelectronic components include a frangible intermediate section. The frangible intermediate section is formed by a region within the lead having weakened mechanical integrity. The frangible intermediate section is made by providing a sacrificial metal layer and forming a projection on the surface of the metal layer from a portion thereof. Lead forming material is deposited onto the surface of the sacrificial metal layer and over the projection. A dielectric layer is formed on the surface of the lead forming material. Upon removing the sacrificial metal layer, a frangible intermediate section is formed within the lead forming material at the location of the projection.
    Type: Grant
    Filed: June 3, 1999
    Date of Patent: April 17, 2001
    Assignee: Tessera, Inc.
    Inventors: Joseph Fjelstad, John W. Smith
  • Patent number: 6205660
    Abstract: Microelectronic contacts, such as flexible, tab-like, cantilever contacts, are provided with asperities disposed in a regular pattern. Each asperity has a sharp feature at its tip remote from the surface of the contact. As mating microelectronic elements are engaged with the contacts, a wiping action causes the sharp features of the asperities to scrape the mating element, so as to provide effective electrical interconnection and, optionally, effective metallurgical bonding between the contact and the mating element upon activation of a bonding material.
    Type: Grant
    Filed: April 22, 1997
    Date of Patent: March 27, 2001
    Assignee: Tessera, Inc.
    Inventors: Joseph Fjelstad, John W. Smith, Thomas H. Distefano, James Zaccardi, A. Christian Walton
  • Patent number: 6208025
    Abstract: A microelectronic component for mounting a rigid substrate, such as a hybrid circuit to a rigid support substrate, such as a printed circuit board. The microelectronic component includes a rigid interposer which may have a chip mounted on its first surface; a pattern of contacts on the rigid interposer; a flexible interposer overlying the second surface of the rigid interposer; a pattern of terminals on the flexible interposer; flexible leads; and solder coated copper balls mounted on the flexible interposer. The microelectronic component may have a socket assembly mounted on the first surface of the rigid interposer. The microelectronic component may be mounted on a rigid support substrate.
    Type: Grant
    Filed: October 6, 1999
    Date of Patent: March 27, 2001
    Assignee: Tessera, Inc.
    Inventors: Pieter H. Bellaar, Thomas H. Distefano, Joseph Fjelstad, Christopher M. Pickett, John W. Smith
  • Patent number: D440266
    Type: Grant
    Filed: September 13, 1998
    Date of Patent: April 10, 2001
    Inventor: John W. Smith
  • Patent number: D442991
    Type: Grant
    Filed: September 13, 2000
    Date of Patent: May 29, 2001
    Assignee: Avery Dennison Corporation
    Inventor: John W. Smith
  • Patent number: D443644
    Type: Grant
    Filed: September 13, 2000
    Date of Patent: June 12, 2001
    Assignee: Avery Dennison Corporation
    Inventors: Charles Richard Lewis, Jr., John W. Smith