Abstract: A microelectronic assembly including elements such as a semiconductor chip and substrate has electrical connections between the elements incorporating fusible conductive metal masses. The fusible masses are surrounded and contained by a compliant material such as an elastomer or gel. The fusible material may melt during operation or processing of the device to relieve thermal cycling stress in the electrical connections.

Abstract: The present invention provides a method for fabricating a compliant microelectronic device package and an associated apparatus for substantially obviating thermal, compliancy and interconnection problems. Flexible, dielectric layers are used having on a first surface a plurality conductive leads which are each electrically coupled at a first end to at least one conductive pad also coupled to the first surface of the dielectric layers. A second end of the conductive leads are further coupled between the dielectric layers across a bonding gap. A compliant layer is then coupled to the bottom surface of the dielectric layers. One of the dielectric layers is coupled to the surface of a die by one of the compliant layer such that the die bond pads are juxtaposed with respective leads in the bonding gap. This assembly is attached to a protective structure and is encapsulated. A solder mask may be placed over the exposed surface of the dielectric layers to cover the leads and prevent shoring.

Abstract: A method of encapsulating a microelectronic assembly comprises providing a microelectronic assembly having an element defining exterior surfaces and an array of terminals exposed at the exterior surfaces. The element defines an aperture through the exterior surfaces. A layer of a curable barrier material is screen printed onto a supporting element. The supporting element is assembled with the microelectronic assembly so that the layer of curable barrier material contacts the exterior surfaces and covers said one or more apertures. An encapsulant is applied to the microelectronic assembly.

Abstract: A method of making a microelectronic package having an array of resilient leads includes providing a first element having a plurality of conductive leads at a first surface thereof, the conductive leads having terminal ends permanently attached to the first element and tip ends remote from the terminal ends, the tip ends being movable relative to the terminal ends. A second element having a plurality of contacts on a first surface thereof is then juxtaposed with the first surface of the first element, and the tip ends of the conductive leads are connected with the contacts of the second microelectronic element. The first and second elements are then moved away from one another so as to vertically extend the conductive leads between the first and second elements. After the moving step, a layer of a spring-like conductive material is formed over the conductive leads to form composite leads.

Abstract: A probe card for testing electronic elements includes a layer of dielectric material provided with a plurality of cavities supported on a substrate. A mass of fusible conductive material having a melting temperature below about 150° C. is disposed in each of said cavities, the dielectric material electrically insulating the masses of fusible conductive material from one another. A probe tip of conductive material having a melting temperature greater than about 150° C. is provided at one common end of each of the masses of fusible conductive material. The probe contacts are separated from an adjacent probe contact by at least one channel formed with the layer of dielectric material.

Abstract: A microelectronic lead element includes an elongated first leg having a surface releasably attached to a substrate. The first leg has a tip end and a base end. An elongated second leg includes a surface releasably attached to a substrate, the second leg having a tip end and a base end. The base end of the first leg is arranged adjacent the base end of the second leg. A body of conductive material is adapted for electrically connecting the base ends of the first and second legs together. The first and second legs extend away from their respective base ends and said body of conductive material in a common direction. Movement of the tip ends relative to each other in a vertical direction relative to the substrate causes flexure of the first and second legs in opposite directions upon release from the substrate.

Abstract: A first microelectronic element is provided with leads having anchor ends connected to contacts and tip ends moveable with respect to the first microelectronic element. The leads can be provided on a carrier sheet that is assembled to the first microelectronic element, or may be formed in situ on the surface of the first element. The leads may be unitary strips of a conductive material, and the anchor ends of the leads may be bonded to the contacts of the first microelectronic element by processes such as thermosonic or ultrasonic bonding. Alternatively, stub leads may be provided on a separate carrier sheet or formed in situ on the front surface of the first microelectronic element, and these stub leads may be connected by wire bonds to the contacts of the first microelectronic element so as to form composite leads. The tip ends of the leads are joined to a second microelectronic element that is moved away from the first microelectronic element so as to deform the leads.

Abstract: An interconnect component comprises a compliant layer having a first surface and a plurality of electrically conductive leads having first ends and extending through the compliant layer. The first ends extend generally parallel to said first surface.

Abstract: A microelectronic component is fabricated by bonding a flexible sheet in tension on a rigid frame so that the sheet spans an aperture in the frame, and performing one or more operations on features on the flexible sheet which will be incorporated into the finished component. The frame maintains dimensional stability of the sheet and aids in regsitration of the sheet with external elements such as processing tools or other parts which are to be assembled with the sheet. Desirably, the frame has a coefficient of thermal expansion different from that of the sheet so that when the sheet is brought from the bonding temperature to the temperature used in processing, differential thermal expansion or contraction will cause increased tension in the sheet.

Abstract: A method of encapsulating a microelectronic assembly comprises providing a microelectronic assembly having an element defining exterior surfaces and an array of terminals exposed at the exterior surfaces. The element defines an aperture through the exterior surfaces. A layer of a curable barrier material is screen printed onto a supporting element. The supporting element is assembled with the microelectronic assembly so that the layer of curable barrier material contacts the exterior surfaces and covers said one or more apertures. An encapsulant is applied to the microelectronic assembly.

Abstract: A method of making a microelectronic assembly including a compliant interface includes providing a first support structure, such as a flexible dielectric sheet, having a first surface and a porous resilient layer on the first surface of the first support structure, stretching the first support structure and bonding the stretched first support structure to a ring structure. The first surface of a second support structure, such as a semiconductor wafer, is then abutted against the porous layer and, desirably after the abutting step, a first curable liquid is disposed between the first and second support structures and within the porous layer. The first curable liquid may then be at least partially cured.

Abstract: Semiconductor chip packages and methods of fabricating the same. The package includes a thermally conductive protective structure having an indentation open to a front side and a flange surface at least partially surrounding the indentation and facing to the front of the structure. A chip is disposed in the indentation so that the front surface of the chip, with contacts thereon, faces toward the front of the structure. A flexible dielectric film having terminals thereon is placed on the flange surface, and a compliant material is disposed between the film and the flange surface. The terminals on the film are connected to the contacts on the chip. The individual terminals on the film are movable with respect to the protective structure, which facilitates mounting and compensation for thermal expansion.

Abstract: A method of connecting a substrate to a semiconductor chip and component therefor to allow for the packaging of a chip even after successive die shrinks. The method compensates for successive die shrinks by providing a substrate that has connection sections of electrical leads that are releasable and/or be displaceable from a surface of the substrate as a result of a force from a bonding tool on the connection sections through at least one substrate aperture. A contact bearing surface of a semiconductor chip may then be aligned with the substrate so that the connection sections are in general alignment with the chip contacts. The connection sections may then be displaced and bonded to respective chip contacts. Other methods may be used to ensure that the chip, after die shrink, fits within the same package such as aligning the chip asymmetrically with the substrate and designing the location and dimensions of the substrate apertures so that the connection sections can be in alignment with the chip contacts.

Abstract: A sheet such as a polymeric dielectric has elongated lead regions partially separated from the main region of the sheet by gaps in the sheet, and has conductors extending along the lead regions. The lead regions are connected to contacts on a microelectronic element, and the microelectronic element is moved away from the main region of the sheet, thereby bending the lead regions downwardly to form leads projecting from the main region of the sheet.

Abstract: A microelectronic assembly including elements such as a semiconductor chip and substrate has electrical connections between the elements incorporating fusible conductive metal masses. The fusible masses are surrounded and contained by a compliant material such as an elastomer or gel. The fusible material may melt during operation or processing of the device to relieve thermal cycling stress in the electrical connections.

Abstract: A semiconductor chip package having an internal laterally curved lead in order to compensate for the CTE mismatch between a semiconductor chip and a supporting substrate, such as a PWB.

Abstract: Multi-layer components such as circuit panels are fabricated by connecting conductive features such as traces one two or more superposed substrates using leads extending through an intermediate dielectric layer. The leads can be closely spaced to provide a high density vertical interconnection, and can be selectively connected to provide customization of the structure.

Abstract: A method of making a microelectronic package having an array of resilient leads includes providing a first element having a plurality of conductive leads at a first surface thereof, the conductive leads having terminal ends permanently attached to the first element and tip ends remote from the terminal ends, the tip ends being movable relative to the terminal ends. A second element having a plurality of contacts on a first surface thereof is then juxtaposed with the first surface of the first element, and the tip ends of the conductive leads are connected with the contacts of the second microelectronic element. The first and second elements are then moved away from one another so as to vertically extend the conductive leads between the first and second elements. After the moving step, a layer of a spring-like conductive material is formed over the conductive leads to form composite leads.

Abstract: A translator for connecting package terminals of a semiconductor chip package to connection pads on a substrate is disclosed. The package terminals are arranged in an array on the semiconductor chip package and the connection pads are arranged in an array on the substrate. The package terminals have a first pitch and the connection pads have a second pitch. The translator has a sheet-like support element with central region and a peripheral region which is more rigid than the central region. First translator terminals are exposed at a first surface of the support element, in the central region. Second translator terminals are exposed at a second surface of the support element, in the peripheral region. The first translator terminals have the first pitch so as to correspond to the package terminals and the second translator terminals have the second pitch so as to correspond to the connection pads. The first and second pitch are different.