Abstract: A home controlled ovarian hyperstimulation method for in vitro fertilization (IVF) or egg freezing and a home IVF kit are described herein.

Abstract: A home controlled ovarian hyperstimulation method for in vitro fertilization (IVF) or egg freezing and a home IVF kit are described herein.

Abstract: A monitoring system that is configured to monitor a property is disclosed. The monitoring system includes a sensor that is configured to generate sensor data that indicates an attribute of the property; a floor sensor that is configured to generate floor sensor data that indicates an amount of pressure applied to a portion of a floor of the property; and a monitor control unit. The monitor control unit is configured to receive, from the sensor, the sensor data; receive, from the floor sensor, the floor sensor data; analyze the sensor data and the floor sensor data; and based on analyzing the sensor data and the floor sensor data, perform a monitoring system action.

Abstract: A semiconductor device includes a first gate stack arranged about a first nanowire and a second nanowire, the first nanowire is arranged above a second nanowire, the first nanowire is connected to a first source/drain region and a second source/drain region. A second gate stack is arranged about a third nanowire and a fourth nanowire, the third nanowire is arranged above a fourth nanowire, the third nanowire is connected to a third source/drain region and a fourth source/drain region. An insulator layer having a first thickness is arranged adjacent to the first gate stack.

Abstract: A home controlled ovarian hyperstimulation method for in vitro fertilization (IVF) or egg freezing and a home IVF kit are described herein.

Abstract: This application provides isolated antibodies, and antigen-binding fragments thereof, that specifically bind Programmed Death Ligand-1 (PD-L1). These PD-L1 antibodies, or antigen-binding fragments thereof, have a high affinity for PD-L1, function to inhibit PD-L1, are less immunogenic compared to their unmodified parent antibodies in a given species (e.g., a human), are capable of increasing T-cell proliferation and IL-2 secretion in a mixed lymphocyte reaction, and can be used to treat human diseases (e.g., cancer, infectious diseases, autoimmune diseases, asthma, transplant rejection, and inflammatory disorders).

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to overlay mark structures and methods of manufacture. The method includes: forming an overlay mark within a layer of a stack of layers; increasing a density of an upper layer of the stack of layers, above the layer, the increased density protecting the overlay mark; and polishing the upper layer or one or more layers above the upper layer of the stack of layers.

Abstract: A method of forming a semiconductor device and resulting structures having nanosheet transistors with sharp junctions by forming a nanosheet stack over a substrate, the nanosheet stack having a plurality of nanosheets alternating with a plurality of sacrificial layers, such that a topmost and a bottommost layer of the nanosheet stack is a sacrificial layer; forming an oxide recess on a first and a second end of each sacrificial layer; and forming a doped extension region on a first and a second end of each nanosheet.

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having self-aligned spacer protection layers. The method includes forming a first sacrificial gate adjacent to a second sacrificial gate on a substrate. A dielectric layer is formed on the substrate and above top surfaces of the first and second sacrificial gates. A self-aligned protection region is formed to cover a first portion of the dielectric layer and a second uncovered portion of the dielectric layer is removed. The first portion of the dielectric layer defines a spacer after the second portion of the dielectric layer is removed.

Abstract: In conjunction with a replacement metal gate (RMG) process for forming a fin field effect transistor (FinFET), gate isolation methods and associated structures leverage the formation of distinct narrow and wide gate cut regions in a sacrificial gate. The formation of a narrow gate cut between closely-spaced fins can decrease the extent of etch damage to interlayer dielectric layers located adjacent to the narrow gate cut by delaying the deposition of such dielectric layers until after formation of the narrow gate cut opening. The methods and resulting structures also decrease the propensity for short circuits between later-formed, adjacent gates.

Abstract: A video processing device which can be implemented as a peripheral device is disclosed. The video processing device is configured to receive one or more videos and audio through a plurality interfaces. Further, the device receives one or more user input corresponding to one or more customization requests of the received video and the audio. The video processing device processes the video and the audio based on the received user input and outputs the processed video and audio via an output interface.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for identifying, at a monitoring system, a location of a device panel, the device panel being configured to communicate with a position module of the monitoring system; obtaining, by the position module, location information for a plurality of anchor devices, each anchor device of the plurality of anchor devices being located within a predefined area of a property; determining, by the position module, a respective location of each anchor device within the predefined area based on analysis of the location information for the plurality of anchor devices; and determining, by the position module, a location for a sensor in the predefined area based on the respective location of at least one anchor device.

Abstract: At least one method, apparatus and system providing semiconductor devices with relatively short gate heights but without a relatively high risk of contact-to-gate shorts. In embodiments, the method, apparatus, and system may provide contact formation by way of self-aligned contact processes.

Abstract: In conjunction with a replacement metal gate (RMG) process for forming a fin field effect transistor (FinFET), gate isolation methods and associated structures leverage the formation of distinct narrow and wide gate cut regions in a sacrificial gate. The formation of a narrow gate cut between closely-spaced fins can decrease the extent of etch damage to interlayer dielectric layers located adjacent to the narrow gate cut by delaying the deposition of such dielectric layers until after formation of the narrow gate cut opening. The methods and resulting structures also decrease the propensity for short circuits between later-formed, adjacent gates.

Abstract: This application provides isolated antibodies, and antigen-binding fragments thereof, that specifically bind Programmed Death 1 (PD-1). These PD-1 antibodies, or antigen-binding fragments thereof, have a high affinity for PD-1, function to inhibit PD-1, are less immunogenic compared to their unmodified parent antibodies in a given species (e.g., a human), are capable of increasing T-cell proliferation and IL-2 secretion in a mixed lymphocyte reaction, and can be used to treat human diseases (e.g., cancer, infectious diseases, autoimmune diseases, asthma, transplant rejection, and inflammatory disorders).

Abstract: At least one method, apparatus and system providing semiconductor devices with relatively short gate heights but without a relatively high risk of contact-to-gate shorts. In embodiments, the method, apparatus, and system may provide contact formation by way of self-aligned contact processes.

Abstract: Devices and methods of fabricating integrated circuit devices for forming uniform nano sheet spacers self-aligned to the channel are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate, multiple layers disposed on the substrate, and at least one gate structure disposed on the multiple layers; depositing an oxide layer over the device; etching the oxide layer to form replacement sidewall spacers positioned on left and right sides of the at least one gate structure; etching the multiple layers to form at least one stack structure; and forming a plurality of recesses within the at least one stack structure. Also disclosed is an intermediate semiconductor, which includes, for instance: a substrate; and at least one stack structure disposed on the substrate, the at least one stack structure having an upper portion and a base portion, wherein a plurality of recesses are located within the base portion.

Abstract: A semiconductor device includes a first gate stack arranged about a first nanowire and a second nanowire, the first nanowire is arranged above a second nanowire, the first nanowire is connected to a first source/drain region and a second source/drain region. A second gate stack is arranged about a third nanowire and a fourth nanowire, the third nanowire is arranged above a fourth nanowire, the third nanowire is connected to a third source/drain region and a fourth source/drain region. An insulator layer having a first thickness is arranged adjacent to the first gate stack.

Abstract: Devices and techniques for initiating and controlling preemptive idle time read scans in a flash based storage system are disclosed. In an example, a memory device includes a NAND memory array and a memory controller to schedule and initiate read scans among multiple locations of the memory array, with such read scans being preemptively triggered during an idle (background) state of the memory device, thus reducing host latency during read and write operations in an active (foreground) state of the memory device. In an example, the optimization technique includes scheduling a read scan operation, monitoring an active or idle state of host IO operations, and preemptively initiating the read scan operation when entering an idle state, before the read scan operation is scheduled to occur. In further examples, the read scan may preemptively occur based on time-based scheduling, frequency-based conditions, or event-driven conditions triggering the read scan.

Abstract: Devices and techniques for initiating and controlling preemptive idle time read scans in a flash based storage system are disclosed. In an example, a memory device includes a NAND memory array and a memory controller to schedule and initiate read scans among multiple locations of the memory array, with such read scans being preemptively triggered during an idle (background) state of the memory device, thus reducing host latency during read and write operations in an active (foreground) state of the memory device. In an example, the optimization technique includes scheduling a read scan operation, monitoring an active or idle state of host IO operations, and preemptively initiating the read scan operation when entering an idle state, before the read scan operation is scheduled to occur. In further examples, the read scan may preemptively occur based on time-based scheduling, frequency-based conditions, or event-driven conditions triggering the read scan.