Patents by Inventor Johnathan E. Faltermeier
Johnathan E. Faltermeier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10332971Abstract: A method of forming a semiconductor structure includes depositing a gate dielectric layer lining a recess of a gate structure formed on a substrate with a first portion of the gate dielectric layer covering sidewalls of the recess and a second portion of the gate dielectric layer covering a bottom of the recess. A protective layer is deposited above the gate dielectric layer and then recessed selectively to the gate dielectric layer so that a top surface of the protective layer is below of the recess. The first portion of the gate dielectric layer is recessed until a top of the first portion of the gate dielectric layer is approximately coplanar with the top surface of the protective layer. The protective layer is removed and a conductive barrier is deposited above the recessed first portion of the gate dielectric layer to cut a diffusion path to the gate dielectric layer.Type: GrantFiled: November 29, 2017Date of Patent: June 25, 2019Assignee: International Business Machines CorporationInventors: Takashi Ando, Johnathan E. Faltermeier, Su Chen Fan, Sivananda K. Kanakasabapathy, Injo Ok, Tenko Yamashita
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Patent number: 10008415Abstract: A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed.Type: GrantFiled: January 30, 2017Date of Patent: June 26, 2018Assignee: International Business Machines CorporationInventors: Xiuyu Cai, Kangguo Cheng, Johnathan E. Faltermeier, Ali Khakifirooz, Theodorus E. Standaert, Ruilong Xie
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Publication number: 20180145150Abstract: A semiconductor structure includes a semiconductor substrate having an outer surface; a plurality of oxide regions, located outward of the outer surface, and defining a plurality of metal-gate-stack-receiving cavities; and a liner interspersed between the plurality of oxide regions and the semiconductor substrate and between the plurality of oxide regions and the plurality of metal-gate-stack-receiving cavities. A layer of high-K material is deposited over the semiconductor structure, including on outer surfaces of the plurality of oxide regions, outer edges of the liner, on walls of the plurality of metal-gate-stack-receiving cavities, and on the outer surface of the semiconductor substrate within the plurality of metal-gate-stack-receiving cavities. The layer of high-K material is chamfered to remove same from the outer surfaces of the plurality of oxide regions, the outer edges of the liner, and partially down the walls of the plurality of metal-gate-stack-receiving cavities.Type: ApplicationFiled: December 30, 2017Publication date: May 24, 2018Inventors: Takashi Ando, Veeraraghavan S. Basker, Johnathan E. Faltermeier, Hemanth Jagannathan, Tenko Yamashita
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Publication number: 20180083117Abstract: A method of forming a semiconductor structure includes depositing a gate dielectric layer lining a recess of a gate structure formed on a substrate with a first portion of the gate dielectric layer covering sidewalls of the recess and a second portion of the gate dielectric layer covering a bottom of the recess. A protective layer is deposited above the gate dielectric layer and then recessed selectively to the gate dielectric layer so that a top surface of the protective layer is below of the recess. The first portion of the gate dielectric layer is recessed until a top of the first portion of the gate dielectric layer is approximately coplanar with the top surface of the protective layer. The protective layer is removed and a conductive barrier is deposited above the recessed first portion of the gate dielectric layer to cut a diffusion path to the gate dielectric layer.Type: ApplicationFiled: November 29, 2017Publication date: March 22, 2018Inventors: Takashi Ando, Johnathan E. Faltermeier, Su Chen Fan, Sivananda K. Kanakasabapathy, Injo Ok, Tenko Yamashita
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Patent number: 9905665Abstract: A method of forming a semiconductor structure includes depositing a gate dielectric layer lining a recess of a gate structure formed on a substrate with a first portion of the gate dielectric layer covering sidewalls of the recess and a second portion of the gate dielectric layer covering a bottom of the recess. A protective layer is deposited above the gate dielectric layer and then recessed selectively to the gate dielectric layer so that a top surface of the protective layer is below of the recess. The first portion of the gate dielectric layer is recessed until a top of the first portion of the gate dielectric layer is approximately coplanar with the top surface of the protective layer. The protective layer is removed and a conductive barrier is deposited above the recessed first portion of the gate dielectric layer to cut a diffusion path to the gate dielectric layer.Type: GrantFiled: March 11, 2016Date of Patent: February 27, 2018Assignee: International Business Machines CorporationInventors: Takashi Ando, Johnathan E. Faltermeier, Su Chen Fan, Sivananda K. Kanakasabapathy, Injo Ok, Tenko Yamashita
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Patent number: 9865703Abstract: A semiconductor structure includes a semiconductor substrate having an outer surface; a plurality of oxide regions, located outward of the outer surface, and defining a plurality of metal-gate-stack-receiving cavities; and a liner interspersed between the plurality of oxide regions and the semiconductor substrate and between the plurality of oxide regions and the plurality of metal-gate-stack-receiving cavities. A layer of high-K material is deposited over the semiconductor structure, including on outer surfaces of the plurality of oxide regions, outer edges of the liner, on walls of the plurality of metal-gate-stack-receiving cavities, and on the outer surface of the semiconductor substrate within the plurality of metal-gate-stack-receiving cavities. The layer of high-K material is chamfered to remove same from the outer surfaces of the plurality of oxide regions, the outer edges of the liner, and partially down the walls of the plurality of metal-gate-stack-receiving cavities.Type: GrantFiled: December 31, 2015Date of Patent: January 9, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Takashi Ando, Veeraraghavan S. Basker, Johnathan E. Faltermeier, Hemanth Jagannathan, Tenko Yamashita
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Patent number: 9735277Abstract: One embodiment provides a method comprising etching a fin of a fin-shaped field effect transistor (FinFET) to form a reduced fin, and laterally etching the reduced fin to form a fin channel including a first fin channel sidewall and a second fin channel sidewall opposing the first fin channel sidewall. The method further comprises forming a first thin dielectric tunnel and a second thin dielectric tunnel on the first fin channel sidewall and the second fin channel sidewall, respectively. Each thin dielectric tunnel prevents lateral epitaxial crystal growth on the fin channel. The method further comprises etching an insulator layer disposed between the fin channel and a substrate of the FinFET to expose portions of a substrate surface of the substrate. A source epitaxy and a drain epitaxy are formed from vertical epitaxial crystal growth on the exposed portions of the substrate surface after epitaxial deposition.Type: GrantFiled: October 27, 2016Date of Patent: August 15, 2017Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Ramachandra Divakaruni, Johnathan E. Faltermeier, Edward J. Nowak, Kern Rim
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Publication number: 20170194459Abstract: A semiconductor structure includes a semiconductor substrate having an outer surface; a plurality of oxide regions, located outward of the outer surface, and defining a plurality of metal-gate-stack-receiving cavities; and a liner interspersed between the plurality of oxide regions and the semiconductor substrate and between the plurality of oxide regions and the plurality of metal-gate-stack-receiving cavities. A layer of high-K material is deposited over the semiconductor structure, including on outer surfaces of the plurality of oxide regions, outer edges of the liner, on walls of the plurality of metal-gate-stack-receiving cavities, and on the outer surface of the semiconductor substrate within the plurality of metal-gate-stack-receiving cavities. The layer of high-K material is chamfered to remove same from the outer surfaces of the plurality of oxide regions, the outer edges of the liner, and partially down the walls of the plurality of metal-gate-stack-receiving cavities.Type: ApplicationFiled: December 31, 2015Publication date: July 6, 2017Inventors: Takashi Ando, Veeraraghavan S. Basker, Johnathan E. Faltermeier, Hemanth Jagannathan, Tenko Yamashita
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Publication number: 20170170323Abstract: One embodiment provides a method comprising etching a fin of a fin-shaped field effect transistor (FinFET) to form a reduced fin, and laterally etching the reduced fin to form a fin channel including a first fin channel sidewall and a second fin channel sidewall opposing the first fin channel sidewall. The method further comprises forming a first thin dielectric tunnel and a second thin dielectric tunnel on the first fin channel sidewall and the second fin channel sidewall, respectively. Each thin dielectric tunnel prevents lateral epitaxial crystal growth on the fin channel. The method further comprises etching an insulator layer disposed between the fin channel and a substrate of the FinFET to expose portions of a substrate surface of the substrate. A source epitaxy and a drain epitaxy are formed from vertical epitaxial crystal growth on the exposed portions of the substrate surface after epitaxial deposition.Type: ApplicationFiled: October 27, 2016Publication date: June 15, 2017Inventors: Kangguo Cheng, Ramachandra Divakaruni, Johnathan E. Faltermeier, Edward J. Nowak, Kern Rim
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Publication number: 20170140994Abstract: A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed.Type: ApplicationFiled: January 30, 2017Publication date: May 18, 2017Inventors: Xiuyu Cai, Kangguo Cheng, Johnathan E. Faltermeier, Ali Khakifirooz, Theodorus E. Standaert, Ruilong Xie
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Patent number: 9633906Abstract: A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed.Type: GrantFiled: January 24, 2014Date of Patent: April 25, 2017Assignees: International Business Machines Corporation, GlobalFoundries, Inc.Inventors: Xiuyu Cai, Kangguo Cheng, Johnathan E. Faltermeier, Ali Khakifirooz, Theodorus E. Standaert, Ruilong Xie
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Patent number: 9559009Abstract: A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed.Type: GrantFiled: October 6, 2015Date of Patent: January 31, 2017Assignees: International Business Machines Corporation, GLOBALFOUNDRIES, INC.Inventors: Xiuyu Cai, Kangguo Cheng, Johnathan E. Faltermeier, Ali Khakifirooz, Theodorus E. Standaert, Ruilong Xie
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Patent number: 9537011Abstract: One embodiment provides a method comprising etching a fin of a fin-shaped field effect transistor (FinFET) to form a reduced fin, and laterally etching the reduced fin to form a fin channel including a first fin channel sidewall and a second fin channel sidewall opposing the first fin channel sidewall. The method further comprises forming a first thin dielectric tunnel and a second thin dielectric tunnel on the first fin channel sidewall and the second fin channel sidewall, respectively. Each thin dielectric tunnel prevents lateral epitaxial crystal growth on the fin channel. The method further comprises etching an insulator layer disposed between the fin channel and a substrate of the FinFET to expose portions of a substrate surface of the substrate. A source epitaxy and a drain epitaxy are formed from vertical epitaxial crystal growth on the exposed portions of the substrate surface after epitaxial deposition.Type: GrantFiled: December 14, 2015Date of Patent: January 3, 2017Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Ramachandra Divakaruni, Johnathan E. Faltermeier, Edward J. Nowak, Kern Rim
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Patent number: 9472408Abstract: A method of reducing a migration of oxygen into a high-k dielectric layer of a semiconducting device is disclosed. An oxide layer of the semiconducting device is deposited on a substrate. A chemical composition of a top portion of the oxide layer is altered. The high-k dielectric layer is deposited on the top portion of the oxide layer to form the semiconducting device. The altered chemical composition of the top portion of the oxide layer reduces migration of oxygen into the high-k dielectric layer.Type: GrantFiled: March 7, 2016Date of Patent: October 18, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Takashi Ando, Veeraraghavan S. Basker, Johnathan E. Faltermeier, Hemanth Jagannathan, Tenko Yamashita
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Patent number: 9412596Abstract: A method of reducing a migration of oxygen into a high-k dielectric layer of a semiconducting device is disclosed. An oxide layer of the semiconducting device is deposited on a substrate. A chemical composition of a top portion of the oxide layer is altered. The high-k dielectric layer is deposited on the top portion of the oxide layer to form the semiconducting device. The altered chemical composition of the top portion of the oxide layer reduces migration of oxygen into the high-k dielectric layer.Type: GrantFiled: January 30, 2015Date of Patent: August 9, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Takashi Ando, Veeraraghavan S. Basker, Johnathan E. Faltermeier, Hemanth Jagannathan, Tenko Yamashita
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Publication number: 20160225628Abstract: A method of reducing a migration of oxygen into a high-k dielectric layer of a semiconducting device is disclosed. An oxide layer of the semiconducting device is deposited on a substrate. A chemical composition of a top portion of the oxide layer is altered. The high-k dielectric layer is deposited on the top portion of the oxide layer to form the semiconducting device. The altered chemical composition of the top portion of the oxide layer reduces migration of oxygen into the high-k dielectric layer.Type: ApplicationFiled: January 30, 2015Publication date: August 4, 2016Inventors: Takashi Ando, Veeraraghavan S. Basker, Johnathan E. Faltermeier, Hemanth Jagannathan, Tenko Yamashita
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Publication number: 20160225629Abstract: A method of reducing a migration of oxygen into a high-k dielectric layer of a semiconducting device is disclosed. An oxide layer of the semiconducting device is deposited on a substrate. A chemical composition of a top portion of the oxide layer is altered. The high-k dielectric layer is deposited on the top portion of the oxide layer to form the semiconducting device. The altered chemical composition of the top portion of the oxide layer reduces migration of oxygen into the high-k dielectric layer.Type: ApplicationFiled: March 7, 2016Publication date: August 4, 2016Inventors: Takashi Ando, Veeraraghavan S. Basker, Johnathan E. Faltermeier, Hemanth Jagannathan, Tenko Yamashita
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Publication number: 20160197157Abstract: A method of forming a semiconductor structure includes depositing a gate dielectric layer lining a recess of a gate structure formed on a substrate with a first portion of the gate dielectric layer covering sidewalls of the recess and a second portion of the gate dielectric layer covering a bottom of the recess. A protective layer is deposited above the gate dielectric layer and then recessed selectively to the gate dielectric layer so that a top surface of the protective layer is below of the recess. The first portion of the gate dielectric layer is recessed until a top of the first portion of the gate dielectric layer is approximately coplanar with the top surface of the protective layer. The protective layer is removed and a conductive barrier is deposited above the recessed first portion of the gate dielectric layer to cut a diffusion path to the gate dielectric layer.Type: ApplicationFiled: March 11, 2016Publication date: July 7, 2016Inventors: Takashi Ando, Johnathan E. Faltermeier, Su Chen Fan, Sivananda K. Kanakasabapathy, Injo Ok, Tenko Yamashita
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Patent number: 9337315Abstract: A FinFET having spacers with a substantially uniform profile along the length of a gate stack which covers a portion of a fin of semiconductor material formed on a substrate is provided by depositing spacer material conformally on both the fins and gate stack and performing an angled ion impurity implant approximately parallel to the gate stack to selectively cause damage to only spacer material deposited on the fin. Due to the damage caused by the angled implant, the spacer material on the fins can be etched with high selectivity to the spacer material on the gate stack.Type: GrantFiled: January 17, 2014Date of Patent: May 10, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Bruce B. Doris, Johnathan E. Faltermeier
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Patent number: 9331174Abstract: A semiconductor substrate including a field effect transistor (FET) and a method of producing the same wherein a stressor is provided in a recess before the source/drain region is formed. The device has an increased carrier mobility in the channel region adjacent to the gate electrode.Type: GrantFiled: April 15, 2010Date of Patent: May 3, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Bruce B. Doris, Johnathan E. Faltermeier, Lahir M. Shaik Adam, Balasubramanian S. Pranatharthi Haran