Patents by Inventor Jon Henri

Jon Henri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8034725
    Abstract: This invention provides a high throughput PECVD process for depositing TEOS films in a multi-station sequential deposition chamber. The methods significantly reduce the number of particles in the TEOS films, thereby eliminating or minimizing small bin defects. The methods of the invention involve dedicating a first station for temperature soak while flowing purge gas. Stopping the flow of reactant gas and flowing the purge gas for station 1 eliminates TEOS condensation on a cold wafer surface and significantly reduces the number of defects in the film, particularly for short temperature soaks.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: October 11, 2011
    Assignee: Novellus Systems, Inc.
    Inventors: Jon Henri, Xingyuan Tang, Jason Tian, Kevin Gerber, Arul N. Dhas
  • Patent number: 7981777
    Abstract: The present invention provides PECVD methods for forming stable and hermetic ashable hard masks (AHMs). The methods involve depositing AHMs using dilute hydrocarbon precursor gas flows and/or high LFRF/HFRF ratios. In certain embodiments, the AHMs are transparent and have high etch selectivities. Single and dual layer hermetic AHM stacks are also provided. According to various embodiments, the dual layer stack includes an underlying AHM layer having tunable optical properties and a hermetic cap layer.
    Type: Grant
    Filed: February 22, 2007
    Date of Patent: July 19, 2011
    Assignee: Novellus Systems, Inc.
    Inventors: Pramod Subramonium, Yongsik Yu, Zhiyuan Fang, Jon Henri
  • Patent number: 7981810
    Abstract: The present invention addresses this need by providing a method for forming transparent PECVD deposited ashable hardmasks (AHMs) that have high plasma etch selectivity to underlying layers. Methods of the invention involve depositing the AHM using dilute hydrocarbon precursor gas flows and/or low process temperatures. The AHMs produced are transparent (having absorption coefficients of less than 0.1 in certain embodiments). The AHMs also have the property of high selectivity of the hard mask film to the underlying layers for successful integration of the film, and are suitable for use with 193 nm generation and below lithography schemes wherein high selectivity of the hard mask to the underlying layers is required. The lower temperature process also allows reduction of the overall thermal budget for a wafer.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: July 19, 2011
    Assignee: Novellus Systems, Inc.
    Inventors: Pramod Subramonium, Zhiyuan Fang, Jon Henri
  • Publication number: 20110146571
    Abstract: A temperature controlled showerhead assembly for chemical vapor deposition (CVD) chambers enhances heat dissipation to provide accurate temperature control of the showerhead face plate and maintain temperatures substantially lower than surrounding components. Heat dissipates by conduction through a showerhead stem and removed by the heat exchanger mounted outside of the vacuum environment. Heat is supplied by a heating element inserted into the steam of the showerhead. Temperature is controlled using feedback supplied by a temperature sensor installed in the stem and in thermal contact with the face plate.
    Type: Application
    Filed: December 18, 2009
    Publication date: June 23, 2011
    Inventors: Christopher M. Bartlett, Ming Li, Jon Henri, Marshall R. Stowell, Mohammed Sabri
  • Patent number: 7955990
    Abstract: Provided herein are improved methods of depositing carbon-based films using acetylene as a precursor. The methods involve using a low-vapor pressure solvent, e.g., dimethylfluoride (DMF) to stabilize the acetylene and delivering the acetylene to a deposition chamber. The methods provide improved wafer-to-wafer thickness uniformity and increase the usable amount of acetylene in an acetylene source to over 95%.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: June 7, 2011
    Assignee: Novellus Systems, Inc.
    Inventors: Jon Henri, Gishun Hsu, Robert Sculac, Scott Stoddard
  • Patent number: 7923376
    Abstract: The present invention provides high deposition rate PECVD methods for depositing TEOS films. The methods significantly reduce the number of particles in the TEOS films, thereby eliminating or minimizing defects. According to various embodiments, the methods involve adding a relatively small amount of helium gas to the process gas. The addition of helium significantly reduces the number of defects in the film, particularly for high deposition rate processes.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: April 12, 2011
    Assignee: Novellus Systems, Inc.
    Inventors: N. Arul Dhas, Jon Henri
  • Patent number: 7915166
    Abstract: Films having high hermeticity and a low dielectric constant can be used as copper diffusion barrier films, etch stop films, CMP stop films and other hardmasks during IC fabrication. Hermetic films can protect the underlying layers, such as layers of metal and dielectric, from exposure to atmospheric moisture and oxygen, thereby preventing undesirable oxidation of metal surfaces and absorption of moisture by a dielectric. Specifically, a bi-layer film having a hermetic bottom layer composed of hydrogen doped carbon and a low dielectric constant (low-k) top layer composed of low-k silicon carbide (e.g., high carbon content hydrogen doped silicon carbide) can be employed. Such bi-layer film can be deposited by PECVD methods on a partially fabricated semiconductor substrate having exposed layers of dielectric and metal.
    Type: Grant
    Filed: February 22, 2007
    Date of Patent: March 29, 2011
    Assignee: Novellus Systems, Inc.
    Inventors: Yongsik Yu, Pramod Subramonium, Zhiyuan Fang, Jon Henri, Elizabeth Apen, Dan Vitkavage
  • Patent number: 7906817
    Abstract: Transistor architectures and fabrication processes generate channel strain without adversely impacting the efficiency of the transistor fabrication process while preserving the material quality and enhancing the performance of the resulting transistor. Transistor strain is generated is PMOS devices using a highly compressive post-salicide amorphous carbon capping layer applied as a blanket over on at least the source and drain regions. The stress from this capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in PMOS channel.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: March 15, 2011
    Assignee: Novellus Systems, Inc.
    Inventors: Qingguo Wu, James S. Sims, Mandyam Sriram, Seshasayee Varadarajan, Haiying Fu, Pramod Subramonium, Jon Henri, Sirish Reddy
  • Publication number: 20100151691
    Abstract: Provided herein are improved methods of depositing carbon-based films using acetylene as a precursor. The methods involve using a low-vapor pressure solvent, e.g., dimethylfluoride (DMF) to stabilize the acetylene and delivering the acetylene to a deposition chamber. The methods provide improved wafer-to-wafer thickness uniformity and increase the usable amount of acetylene in an acetylene source to over 95%.
    Type: Application
    Filed: December 12, 2008
    Publication date: June 17, 2010
    Applicant: Novellus Systems Inc.
    Inventors: Jon Henri, Gishun Hsu, Robert Sculac, Scott Stoddard
  • Patent number: 7704894
    Abstract: This invention provides a high throughput PECVD process for depositing TEOS films in a multi-station sequential deposition chamber. The methods significantly reduce the number of particles in the TEOS films, thereby eliminating or minimizing small bin defects. The methods of the invention involve dedicating a first station for temperature soak while flowing purge gas. Stopping the flow of reactant gas and flowing the purge gas for station 1 eliminates TEOS condensation on a cold wafer surface and significantly reduces the number of defects in the film, particularly for short temperature soaks.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: April 27, 2010
    Assignee: Novellus Systems, Inc.
    Inventors: Jon Henri, Xingyuan Tang, Jason Tian, Kevin Gerber, Arul N. Dhas
  • Patent number: 7381644
    Abstract: A method for forming a PECVD deposited ashable hardmask (AHM) with less than 30% H content at a process temperature below 500° C., e.g., about 400° C. produces low H content hard masks having the property of high selectivity of the hard mask film to the underlying layers for successful integration of the film, and are suitable for use with 193 nm generation and below lithography schemes wherein high selectivity of the hard mask to the underlying layers is required. The low temperature, low H films are produced by use of a pulsed film hydrocarbon precursor plasma treatment that reduces the amount of hydrogen incorporated in the film and therefore drives down the etch rate of the hard mask thus increasing the selectivity. The lower temperature process also allows reduction of the overall thermal budget for a wafer.
    Type: Grant
    Filed: December 23, 2005
    Date of Patent: June 3, 2008
    Assignee: Novellus Systems, Inc.
    Inventors: Pramod Subramonium, Zhiyuan Fang, Jon Henri
  • Patent number: 6821407
    Abstract: An electroplating system includes (a) a phosphorized anode having an average grain size of at least about 50 micrometers and (b) plating apparatus that separates the anode from the cathode and prevents most particles generated at the anode from passing to the cathode. The separation may be accomplished by interposing a microporous chemical transport barrier between the anode and cathode. The relatively few particles that are generated at the large grain phosphorized copper anode are prevented from passing into the cathode (wafer) chamber area and thereby causing a defect in the part.
    Type: Grant
    Filed: August 27, 2002
    Date of Patent: November 23, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, Timothy Mark Archer, Thomas Tan Vu, Seshasayee Varadarajan, Jon Henri, Steven T. Mayer, David Sauer, Anita Kang, Gerald Feldewerth
  • Patent number: 6793796
    Abstract: Electroplating methods using an electroplating bath containing metal ions and a suppressor additive, an accelerator additive, and a leveler additive, together with controlling the current density applied to a substrate, avoid defects in plated films on substrates having features with a range of aspect ratios, while providing good filling and thickness distribution. The methods include, in succession, applying DC cathodic current densities optimized to form a conformal thin film on a seed layer, to provide bottom-up filling, preferentially on features having the largest aspect ratios, and to provide conformal plating of all features and adjacent field regions. Including a leveling agent in the electroplating bath produces films with better quality after subsequent processing.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: September 21, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, David Smith, Steven T. Mayer, Jon Henri, Sesha Varadarajan
  • Patent number: 6524956
    Abstract: A chemical vapor deposition process for depositing tungsten films having small grain size is provided. The process involves depositing a nucleation layer having very small nuclei that are closely spaced so that there are few vacancies on the surface. Such a nucleation layer results in a film with small grains after the subsequent deposition of bulk layers. The temperature of the substrate can be increased during deposition of the nucleation layer and then lowered for deposition of the bulk layer to produce a small grain tungsten film. Additionally, the thickness of the nucleation layer can be controlled, and the deposition chamber pressure and silage flow rates can also be controlled to achieve the desired nucleation layer before deposition of the bulk layers.
    Type: Grant
    Filed: September 22, 2000
    Date of Patent: February 25, 2003
    Assignee: Novelius Systems, Inc.
    Inventors: Jason Tian, Jon Henri
  • Patent number: 6440291
    Abstract: Methods and apparatus are used for triggering and controlling an initial induction period in which a substrate is immersed in an electrochemical bath prior to actual electrochemical processing. This is accomplished by sensing a change in cell potential upon immersion of the substrate or a counter electrode in an electrochemical bath. Appropriate logic then holds the cell potential or current at a fixed value for a defined delay period. After that period ends, the logic allows the cell potential or current to increase to a level where electrochemical processing begins.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: August 27, 2002
    Assignee: Novellus Systems, Inc.
    Inventors: Jon Henri, John Floyd Ostrowski
  • Publication number: 20010015321
    Abstract: Electroplating methods using an electroplating bath containing metal ions and a suppressor additive, an accelerator additive, and a leveler additive, together with controlling the current density applied to a substrate, avoid defects in plated films on substrates having features with a range of aspect ratios, while providing good filling and thickness distribution. The methods include, in succession, applying DC cathodic current densities optimized to form a conformal thin film on a seed layer, to provide bottom-up filling, preferentially on features having the largest aspect ratios, and to provide conformal plating of all features and adjacent field regions. Including a leveling agent in the electroplating bath produces films with better quality after subsequent processing.
    Type: Application
    Filed: February 28, 2001
    Publication date: August 23, 2001
    Inventors: Jonathan D. Reid, David Smith, Steven T. Mayer, Jon Henri, Sesha Varadarajan
  • Patent number: 5176790
    Abstract: An improved process is described for forming one or more vias through an insulation layer by plasma etching to an underlying metal layer without depositing etch residues, including metal sputtered from the underlying metal layer, onto the sidewalls of the vias, which comprises, in one embodiment, using in the gaseous etchant one or more 3-6 carbon fluorinated hydrocarbons having the formula C.sub.x H.sub.y F.sub.z, wherein x is 3 to 6, y is 0 to 3, and z is 2x-y when the fluorinated hydrocarbon is cyclic and z is 2x-y+2 when the fluorinated hydrocarbon is noncyclic. One or more other fluorine-containing gases may also be used as long as the 3-6 carbon fluorinated hydrocarbons comprise at least 10 volume % of the fluorine-containing gas mixture. The fluorinated hydrocarbon gas or fluorine-containing gas mixture also may be mixed with up to 90 volume % total of one or more inert gases to control the taper of the via walls.
    Type: Grant
    Filed: September 25, 1991
    Date of Patent: January 5, 1993
    Assignee: Applied Materials, Inc.
    Inventors: Paul Arleo, Jon Henri, Graham Hills, Jerry Wong, Robert Wu