Abstract: A nanostructured device according to the invention comprises a first group of nanowires protruding from a substrate where each nanowire of the first group of nanowires comprises at least one pn- or p-i-n-junction. A first contact, at least partially encloses and is electrically connected to a first side of the pn- or p-i-n-junction of each nanowire in the first group of nanowires. A second contacting means comprises a second group of nanowires that protrudes from the substrate, and is arranged to provide an electrical connection to a second side of the pn- or p-i-n-junction.

Abstract: The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (28) in semiconductor structures comprising a substrate (10) and an elongated structure (5) essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device (1) is utilized in combination with either anisotropic desposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.

Abstract: The present invention provides a substrate (1) with a bulk layer (3) and a buffer layer (4) having a thickness of less than 2 ?m arranged on the bulk layer (3) for growth of a multitude of nanowires (2) oriented in the same direction on a surface (5) of the buffer layer (4). A nanowire structure, a nanowire light emitting diode comprising the substrate (1) and a production method for fabricating the nanowire structure is also provided. The production method utilizes non-epitaxial methods for forming the buffer layer (4).

Abstract: The present invention provides a method for aligning nanowires which can be used to fabricate devices comprising nanowires that has well-defined and controlled orientation independently on what substrate they are arranged on. The method comprises the steps of providing nanowires (1) and applying an electrical field (E) over the population of nanowires (1), whereby an electrical dipole moment of the nanowires makes them align along the electrical field (E). Preferably the nanowires are dispersed in a fluid during the steps of providing and aligning. When aligned, the nanowires can be fixated, preferably be deposition on a substrate (2). The electrical field can be utilised in the deposition. Pn-junctions or any net charge introduced in the nanowires (1) may assist in the aligning and deposition process. The method is suitable for continuous processing, e.g. in a roll-to-roll process, on practically any substrate materials and not limited to substrates suitable for particle assisted growth.

Abstract: A resonant tunneling diode, and other one dimensional electronic, photonic structures, and electromechanical MEMS devices, are formed as a heterostructure in a nanowhisker by forming length segments of the whisker with different materials having different band gaps.

Abstract: The present invention relates to semiconductor devices comprising semiconductor nanoelements. In particular the invention relates to devices having a volume element having a larger diameter than the nanoelement arranged in epitaxial connection to the nanoelement. The volume element is being doped in order to provide a high charge carrier injection into the nanoelement and a low access resistance in an electrical connection. The nanoelement may be upstanding from a semiconductor substrate. A concentric layer of low resistivity material forms on the volume element forms a contact.

Abstract: A resonant tunneling diode, and other one dimensional electronic, photonic structures, and electromechanical MEMS devices, are formed as a heterostructure in a nanowhisker by forming length segments of the whisker with different materials having different band gaps.

Abstract: Outer-loop power control methods and apparatus are disclosed. In an exemplary embodiment, a short-term block error rate is measured for a received signal, and a coarse adjustment to a target signal-to-interference ratio (SIR) is calculated as a function of the short-term block error rate, a target block error rate, and a first loop tuning parameter. In some embodiments, a fine adjustment to the target SIR is also calculated, as a function of a smoothed block error rate, the target block error rate, and a second loop tuning parameter. The coarse adjustment provides quick responsiveness to received block errors, while the fine adjustment moderates the coarse adjustments by accounting for a longer-term view of the received block error rate. The target SIR adjustments disclosed herein may be computed in each of several iterations of an outer-loop power control loop.

Abstract: The present invention relates to light emitting diodes comprising at least one nanowire. The LED according to the invention is an upstanding nanostructure with the nanowire protruding from a substrate. A bulb with a larger diameter than the nanowire is arranged in connection to the nanowire and at an elevated position with regards to the substrate. A pn-junction is formed by the combination of the bulb and the nanowire resulting in an active region to produce light.

Abstract: Outer-loop power control methods and apparatus are disclosed. In an exemplary embodiment, a short-term block error rate is measured for a received signal, and a coarse adjustment to a target signal-to-interference ratio (SIR) is calculated as a function of the short-term block error rate, a target block error rate, and a first loop tuning parameter. In some embodiments, a fine adjustment to the target SIR is also calculated, as a function of a smoothed block error rate, the target block error rate, and a second loop tuning parameter. The coarse adjustment provides quick responsiveness to received block errors, while the fine adjustment moderates the coarse adjustments by accounting for a longer-term view of the received block error rate. The target SIR adjustments disclosed herein may be computed in each of several iterations of an outer-loop power control loop.

Abstract: Outer-loop power control methods and apparatus are disclosed. In an exemplary embodiment, a short-term block error rate is measured for a received signal, and a coarse adjustment to a target signal-to-interference ratio (SIR) is calculated as a function of the short-term block error rate, a target block error rate, and a first loop tuning parameter. In some embodiments, a fine adjustment to the target SIR is also calculated, as a function of a smoothed block error rate, the target block error rate, and a second loop tuning parameter. The coarse adjustment provides quick responsiveness to received block errors, while the fine adjustment moderates the coarse adjustments by accounting for a longer-term view of the received block error rate. The target SIR adjustments disclosed herein may be computed in each of several iterations of an outer-loop power control loop.

Abstract: The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (28) in semiconductor structures comprising a substrate (10) and an elongated structure (5) essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device (1) is utilized in combination with either anisotropic desposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.

Abstract: Nano-engineered structures are disclosed, incorporating nanowhiskers of high mobility conductivity and incorporating pn junctions. In one embodiment, a nanowhisker of a first semiconducting material has a first band gap, and an enclosure comprising at least one second material with a second band gap encloses said nanoelement along at least part of its length, the second material being doped to provide opposite conductivity type charge carriers in respective first and second regions along the length of the of the nanowhisker, whereby to create in the nanowhisker by transfer of charge carriers into the nanowhisker, corresponding first and second regions of opposite conductivity type charge carriers with a region depleted of free carriers therebetween.

Abstract: The present invention relates to light emitting diodes comprising at least one nanowire. The LED according to the invention is an upstanding nanostructure with the nanowire protruding from a substrate. A bulb with a larger diameter than the nanowire is arranged in connection to the nanowire and at an elevated position with regards to the substrate. A pn-junction is formed by the combination of the bulb and the nanowire resulting in an active region to produce light.

Abstract: The present invention provides a nanostructured memory device comprising at least one semiconductor nanowire (3) forming a current transport channel, one or more shell layers (4) arranged around at least a portion of the nanowire (3), and nano-sized charge trapping centers (10) embedded in said one or more shell layers (4), and one or more gate electrodes (14) arranged around at least a respective portion of said one or more shell layers (4). Preferably said one or more shell layers (4) are made of a wide band gap material or an insulator. The charge trapping centers (10) may be charged/written by using said one or more gate electrodes (14) and a change in an amount of charge stored in one or more of the charge trapping centers (10) alters the conductivity of the nanowire (3).

Abstract: The present invention relates to growth of III-V semiconductor nanowires (2) on a Si substrate (3). Controlled vertical nanowire growth is achieved by a step, to be taken prior to the growing of the nanowire, of providing group III or group V atoms to a (111) surface of the Si substrate to provide a group III or group V 5 surface termination (4). A nanostructured device comprising a plurality of aligned III-V semiconductor nanowires (2) grown on, and protruding from, a (111) surface of a Si substrate (3) in an ordered pattern in compliance with a predetermined device layout is also presented.

Abstract: Nano-engineered structures are disclosed, incorporating nanowhiskers of high mobility conductivity and incorporating pn junctions. In one embodiment, a nanowhisker of a first semiconducting material has a first band gap, and an enclosure comprising at least one second material with a second band gap encloses said nanoelement along at least part of its length, the second material being doped to provide opposite conductivity type charge carriers in respective first and second regions along the length of the of the nanowhisker, whereby to create in the nanowhisker by transfer of charge carriers into the nanowhisker, corresponding first and second regions of opposite conductivity type charge carriers with a region depleted of free carriers therebetween.

Abstract: The present invention relates to light emitting diodes, LEDs. In particular the invention relates to a LED comprising a nanowire as an active component. The nanostructured LED according to the embodiments of the invention comprises a substrate and at an upstanding nanowire protruding from the substrate. A pn-junction giving an active region to produce light is present within the structure. The nanowire, or at least a part of the nanowire, forms a wave-guiding section directing at least a portion of the light produced in the active region in a direction given by the nanowire.

Abstract: The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (28) in semiconductor structures comprising a substrate (10) and an elongated structure (5) essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device (1) is utilized in combination with either anisotropic deposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.

Abstract: The present invention provides an optoelectronic semiconductor device comprising at least one semiconductor nanowire, wherein the nanowire comprises a nanowire core and at least one shell layer arranged around at least a portion of the nanowire core. The nanowire core and the shell layer form a pn or pin junction that in operation provides an active region for carrier generation or carrier recombination. Quantum dots adapted to act as carrier recombination centres or carrier generation centres are arranged in the active region. By using the nanowire core as template for formation of the quantum dots and the shell layer, quantum dots of homogeneous size and uniform distribution can be obtained. Basically, the optoelectronic semiconductor device can be used for light generation or light absorption.