Patents by Inventor Jonathan D. Bradbury

Jonathan D. Bradbury has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10338918
    Abstract: A Vector Galois Field Multiply Sum and Accumulate instruction. Each element of a second operand of the instruction is multiplied in a Galois field with the corresponding element of the third operand to provide one or more products. The one or more products are exclusively ORed with each other and exclusively ORed with a corresponding element of a fourth operand of the instruction. The results are placed in a selected operand.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: July 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Jonathan D. Bradbury
  • Patent number: 10331408
    Abstract: An instruction to perform a multiply and shift operation is executed. The executing includes multiplying a first value and a second value obtained by the instruction to obtain a product. The product is shifted in a specified direction by a user-defined selected amount to provide a result, and the result is placed in a selected location. The result is to be used in processing within the computing environment.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: June 25, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Steven R. Carlough, Reid T. Copeland, Silvia Melitta Mueller
  • Patent number: 10333548
    Abstract: Systems, methods, and computer-readable media are described for performing data compression in a manner that does not require software to make a call to hardware to close a compressed data block, thereby reducing computational overhead. In response to a request from software to data compression hardware for a data encoding, the hardware may return the data encoding as well as an end-of-block symbol encoding value and bit length. The hardware may load the end-of-block symbol encoding value and bit length into a different area in the returned structure such that the software has direct access to the value. When the software determines that a block should be closed, the software may retrieve the end-of-block symbol and insert it into the block without needing to make a call to hardware. The software may then make a call to the hardware to request a new data encoding for subsequent compressed data blocks.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: June 25, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony T. Sofia, Jonathan D. Bradbury, Matthias Klein, Bruce Giamei
  • Patent number: 10318430
    Abstract: Embodiments relate to a system operation queue for a transaction. An aspect includes determining whether a system operation is part of an in-progress transaction of a central processing unit (CPU). Another aspect includes based on determining that the system operation is part of the in-progress transaction, storing the system operation in a system operation queue corresponding to the in-progress transaction. Yet another aspect includes, based on the in-progress transaction ending, processing the system operation in the system operation queue.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Michael K. Gschwind, Eric M. Schwarz
  • Patent number: 10318299
    Abstract: A read operation is initiated to obtain a wide input operand. Based on the initiating, a determination is made as to whether the wide input operand is available in a wide register or in two narrow registers. Based on determining the wide input operand is not available in the wide register, merging at least a portion of contents of the two narrow registers to obtain merged contents, writing the merged contents into the wide register, and continuing the read operation to obtain the wide input operand. Based on determining the wide input operand is available in the wide register, obtaining the wide input operand from the wide register.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Michael K. Gschwind
  • Patent number: 10310855
    Abstract: Embodiments relate to non-default instruction handling within a transaction. An aspect includes entering a transaction, the transaction comprising a first plurality of instructions and a second plurality of instructions, wherein a default manner of handling of instructions in the transaction is one of atomic and non-atomic. Another aspect includes encountering a non-default specification instruction in the transaction, wherein the non-default specification instruction comprises a single instruction that specifies the second plurality of instructions of the transaction for handling in a non-default manner comprising one of atomic and non-atomic, wherein the non-default manner is different from the default manner. Another aspect includes handling the first plurality of instructions in the default manner. Yet another aspect includes handling the second plurality of instructions in the non-default manner.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: June 4, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Michael K. Gschwind, Maged M. Michael, Eric M. Schwarz, Valentina Salapura, Chung-Lung K. Shum
  • Publication number: 20190163561
    Abstract: A method includes initiating a power on sequence of a computer equipment including a plurality of sensors at a serviceable location within a component of the computer equipment, the plurality of sensors communicating with a sensor monitor coupled with an interlock mechanism, and a service console capable of communicating with the sensor monitor, receiving feedback data from the plurality of sensors during the power on sequence, each of the plurality of sensors is detecting a physical condition at the serviceable location, determining whether the feedback data exceeds a predefined threshold value, the feedback data exceeding the predefined threshold value is associated with a fault at a serviceable location, in response to the feedback data exceeding the predefined threshold value, logging the fault at the serviceable location, aborting the power on sequence of the equipment, and prompting an equipment servicer of the fault at the serviceable location.
    Type: Application
    Filed: November 29, 2017
    Publication date: May 30, 2019
    Inventors: Jonathan D. Bradbury, Jonathan R. Fry, Michael R. Kane, Jeffrey Nettey
  • Publication number: 20190163492
    Abstract: A stack accelerator is employed for stack-type accesses. An instruction stream is scanned for stack-type accesses. These stack-type accesses may include push and pop stack operations. Based on identifying a stack-type access in the instruction stream, memory operations are replaced with one or more operations that access a stack in a stack accelerator.
    Type: Application
    Filed: November 28, 2017
    Publication date: May 30, 2019
    Inventors: Michael K. Gschwind, Chung-Lung K. Shum, Timothy J. Slegel, Jonathan D. Bradbury
  • Patent number: 10303759
    Abstract: A method, computer program product, and system includes a processor obtaining data including values and generating a value conversion dictionary by applying a parse tree based compression algorithm to the data, where the value conversion dictionary includes dictionary entries that represent the values. The processor obtains a distribution of the values and estimates a likelihood for each based on the distribution. The processor generates a code word to represent each value, a size of each code word is inversely proportional to the likelihood of the word. The processor assigns a rank to each code word, the rank for each represents the likelihood of the value represented by the code word; and based on the rank associated with each code word, the processor reorders each dictionary entry in the value conversion dictionary to associate each dictionary entry with an equivalent rank, the reordered value conversion dictionary comprises an architected dictionary.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jonathan D. Bradbury, Markus Helms, Christian Jacobi, Aditya N. Puranik, Christian Zoellin
  • Publication number: 20190155602
    Abstract: A Vector Floating Point Test Data Class Immediate instruction is provided that determines whether one or more elements of a vector specified in the instruction are of one or more selected classes and signs. If a vector element is of a selected class and sign, an element in an operand of the instruction corresponding to the vector element is set to a first defined value, and if the vector element is not of the selected class and sign, the operand element corresponding to the vector element is set to a second defined value.
    Type: Application
    Filed: January 21, 2019
    Publication date: May 23, 2019
    Inventors: Jonathan D. Bradbury, Eric M. Schwarz
  • Publication number: 20190138219
    Abstract: Processing within a computing environment is facilitated by ascertaining locality domain information of a unit of memory to processing capability within the computing environment. Once ascertained, the locality domain information of the unit of memory may be cached in a data structure to facilitate one or more subsequent lookups of the locality domain information associated with one or more affinity evaluations of the unit of memory to processing capability of the computing environment.
    Type: Application
    Filed: November 9, 2017
    Publication date: May 9, 2019
    Inventors: Michael K. GSCHWIND, Jonathan D. BRADBURY
  • Patent number: 10282305
    Abstract: Selective purging of entries of structures associated with address translation. A request to purge entries of a structure associated with address translation is obtained. Based on obtaining the request, a determination is made as to whether selective purging of the structure associated with address translation is to be performed. Based on determining that selective purging is to be performed, one or more entries of the structure associated with address translation are purged. The selectively purging includes clearing the one or more entries of the structure associated with address translation for a host of the computing environment and leaving one or more entries of one or more guest operating systems in the structure associated with address translation. The one or more guest operating systems are managed by the host.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: May 7, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christian Borntraeger, Jonathan D. Bradbury, Lisa Cranton Heller, Christian Jacobi, Martin Schwidefsky
  • Patent number: 10282276
    Abstract: Techniques relate to fingerprint-initiated trace extraction. A determination is made of whether a fingerprint is present in software that is currently executing on a processor of a computer system. The fingerprint comprises a representation of a sequence of behavior that occurs in the processor while the software is executing. In response to determining that the fingerprint is not present in the software currently executing on the processor, monitoring continues for the software executing on the processor to determine whether the fingerprint is present. In response to determining that the fingerprint is present in the software executing on the processor, a trace is triggered of a code segment of the software corresponding to when the fingerprint is recognized. The trace is for a record of instructions of the code segment of the software.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: May 7, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Giles R. Frazier, Michael Karl Gschwind, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum
  • Patent number: 10275246
    Abstract: A method for implementing a programmable linear feedback shift register instruction, the method includes obtaining, by a processor, the machine instruction for execution, the machine instruction includes a first input operand indicating the current value of a shift register, wherein the shift register includes a data bit for each of a plurality of cells, a second input operand indicating a first sub-set of cells from the plurality of cells, and a logical operation specifier field indicating a logical operation to perform on the first and second input operands. Additionally, executing the machine instruction includes performing the logical operation based on the first input operand, the second input operand, and the logical operation specifier field, and generating an output operand by shifting the current value of the shift register to vacate a cell of the shift register and inserting an output value of the logical operation into the vacated cell of the shift register.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: April 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Steven R. Carlough, Brian R. Prasky, Eric M. Schwarz
  • Patent number: 10270773
    Abstract: One or more transactions may request or be assigned tokens within a transactional memory environment. A transaction may be created by at least one thread. A first transaction that includes a first token type may be received. A request may be received for a for a potential conflict check between the first transaction and a second transaction. In response to receiving the transaction potential conflict check, the first transaction and the second transaction are determined to be conflicting or not conflicting. The second transaction is assigned a token type in response to the determination of the transaction potential conflict check between the first transaction and the second transaction.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: April 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jonathan D. Bradbury, Fadi Y. Busaba, Michael Karl Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum
  • Patent number: 10270775
    Abstract: One or more transactions may request or be assigned tokens within a transactional memory environment. A transaction may be created by at least one thread. A first transaction that includes a first token type may be received. A request may be received for a for a potential conflict check between the first transaction and a second transaction. In response to receiving the transaction potential conflict check, the first transaction and the second transaction are determined to be conflicting or not conflicting. The second transaction is assigned a token type in response to the determination of the transaction potential conflict check between the first transaction and the second transaction.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: April 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jonathan D. Bradbury, Fadi Y. Busaba, Michael Karl Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum
  • Publication number: 20190107446
    Abstract: Embodiments of the invention include a fracture ring sensor and a method of using the same to detect out of tolerance forces. Aspects of the invention include a product having a defined an out of tolerance force, a fracture ring sensor, and a mounting assembly coupling the fracture ring sensor to the product. The fracture ring sensor is patterned with a conductive trace and is manufactured to break when subjected to a predetermined amount of force. The predetermined amount of force is substantially equal to a percentage of the out of tolerance force of the product.
    Type: Application
    Filed: November 9, 2017
    Publication date: April 11, 2019
    Inventors: Jonathan D. Bradbury, Jonathan R. Fry, Michael R. Kane
  • Publication number: 20190107445
    Abstract: Embodiments of the invention include a fracture ring sensor and a method of using the same to detect out of tolerance forces. Aspects of the invention include a product having a defined an out of tolerance force, a fracture ring sensor, and a mounting assembly coupling the fracture ring sensor to the product. The fracture ring sensor is patterned with a conductive trace and is manufactured to break when subjected to a predetermined amount of force. The predetermined amount of force is substantially equal to a percentage of the out of tolerance force of the product.
    Type: Application
    Filed: October 5, 2017
    Publication date: April 11, 2019
    Inventors: Jonathan D. Bradbury, Jonathan R. Fry, Michael R. Kane
  • Publication number: 20190108135
    Abstract: Increasing the scope of local purges of structures associated with address translation. A hardware thread of a physical core of a machine configuration issues a purge request. A determination is made as to whether the purge request is a local request. Based on the purge request being a local request, entries of a structure associated with address translation are purged on at least multiple hardware threads of a set of hardware threads of the the machine configuration.
    Type: Application
    Filed: December 7, 2018
    Publication date: April 11, 2019
    Inventors: Jonathan D. Bradbury, Fadi Y. Busaba, Lisa Cranton Heller
  • Patent number: 10255189
    Abstract: A transactional memory execution environment receives a first request from a first transaction to access a cache line. A first request is received from a first transaction to access a cache line. The cache line is determined to be used by a second transaction. The first transaction and the second transaction opt-in to a transaction potential conflict check. The transaction potential conflict check determines if the first transaction and the second transaction are in a conflicting coherent state. The conflicting coherent state occurs when the first transaction is modifying the cache line used by the second transaction. The first transaction is allowed access to the cache line without aborting the second transaction in response to a determination that the first transaction and the second transaction are compatible from the transaction potential conflict check.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jonathan D. Bradbury, Fadi Y. Busaba, Michael Karl Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum