Abstract: Instruction interrupt suppression for an overflow condition. An instruction is executed, and a determination is made that an overflow condition occurred. Based on a per-instruction overflow interrupt indicator being set to a defined value, interrupt processing for the overflow condition is performed, and based on the per-instruction overflow interrupt indicator being set to another defined value, the interrupt processing for the overflow condition is bypassed.

Abstract: An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers.

Abstract: An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers. The system firmware includes a retry buffer and the core includes an analysis and retry logic.

Abstract: An input/output store instruction is handled. A data processing system includes a system nest communicatively coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is communicatively coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to an external device which is communicatively coupled to the input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed.

Abstract: A computer system includes a hardware controller and a host system. The hardware controller includes an accelerator to encode a data stream requested by an application based on a version of the accelerator. The host system executes a compression library linked to the application. The compression library operates according to one or more behavior characteristics to execute a compression algorithm that compresses the encoded data provided by the hardware controller. The behavior characteristics of the compression library is actively changed based on the version of the accelerator.

Abstract: A method includes initiating a power on sequence of a computer equipment including a plurality of sensors at a serviceable location within a component of the computer equipment, the plurality of sensors communicating with a sensor monitor coupled with an interlock mechanism, and a service console capable of communicating with the sensor monitor, receiving feedback data from the plurality of sensors during the power on sequence, each of the plurality of sensors is detecting a physical condition at the serviceable location, determining whether the feedback data exceeds a predefined threshold value, the feedback data exceeding the predefined threshold value is associated with a fault at a serviceable location, in response to the feedback data exceeding the predefined threshold value, logging the fault at the serviceable location, aborting the power on sequence of the equipment, and prompting an equipment servicer of the fault at the serviceable location.

Abstract: An embodiment of the invention may include a method, computer program product and system for guided service procedure. The embodiment may include receiving feedback data from one or more of a plurality of sensors. Each of the plurality of sensors may detect a physical condition at a serviceable location within an item of equipment. The item of equipment may be undergoing a service procedure by an equipment servicer. The embodiment may include determining whether the received feedback data from one or more of the plurality of sensors exceeds a threshold value. Based on determining that the threshold value is exceeded, the embodiment may include alerting the equipment servicer during the service procedure.

Abstract: An electro-mechanical fuse is provided and includes a chassis component, an extrusion disposed on a monitored component which is disposable proximate to the chassis component and a sensor. The sensor is mounted to the chassis component. The sensor is mechanically breakable in power-on and power-off conditions by the extrusion as a result of a predefined action of or relative to the monitored component. The sensor electrically signals an occurrence of the mechanical breakage during power-on conditions following mechanical breakage.

Abstract: A secure cloud computing environment protects the confidentiality of application code from a customer while simultaneously protecting the confidentiality of a customer's data from intentional or inadvertent leaks by the application code. This result is accomplished without the need to trust the application code and without requiring human surveillance or intervention. A client secure virtual machine (SVM) is accessible by a client who supplies commands, operand data and application data. An appliance SVM has the application code loaded therein and includes an application program interface that accesses a memory area shared by both SVMs. All access to the appliance SVM is initially revoked by an ultravisor, except for the shared memory. The appliance SVM processes the commands without ever saving any persistent state of the application data. The ultravisor manages an SVM by maintaining exclusive control over a device tree used by the operating system of the SVM.

Abstract: An aspect includes a system architecture that includes a processing unit, an accelerator, a main source buffer, a main target buffer, and a memory block. The main source buffer stores a first part of a source symbol received from an external source. The main target buffer stores an output symbol received from the accelerator. The memory block includes an overflow source buffer that stores the first part of the source symbol received from the main source buffer. The accelerator fetches the first part of the source symbol stored in the overflow source buffer and a second part of the source symbol stored in the main source buffer, and converts the first and second parts of the source symbol together into the output symbol. The second part of the source symbol includes a part of the source symbol not included in the first part of the source symbol.

Abstract: Embodiments are directed to a computer implemented method for executing machine instructions in a central processing unit. The method includes obtaining, by a processor system, a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture. The method further includes executing the machine instruction, wherein the executing includes loading a multiplicand into a multiplicand register, and loading a multiplier into a multiplier register. The executing further generates an intermediate product having least significant bits by multiplying the multiplicand and the multiplier. The executing further includes generating a rounded product by performing a probability analysis on the least significant bits of the intermediate product, and initiating a rounding operation on the intermediate product to produce the rounded product based at least in part on the probability analysis.

Abstract: A Vector Floating Point Test Data Class Immediate instruction is provided that determines whether one or more elements of a vector specified in the instruction are of one or more selected classes and signs. If a vector element is of a selected class and sign, an element in an operand of the instruction corresponding to the vector element is set to a first defined value, and if the vector element is not of the selected class and sign, the operand element corresponding to the vector element is set to a second defined value.

Abstract: An opto-mechanical fuse is provided. The opto-mechanical fuse includes a chassis component, an extrusion disposed on a monitored component proximate to the chassis component and a sensor. The sensor includes an optical conductor mounted to the chassis component to assume one of an optically transmitting state and an optically non-transmitting state in both power-on and power-off conditions. An assumption of the optically non-transmitting state by the optical conductor occurs due to an interaction of the optical conductor and the extrusion resulting from a predefined magnitude of deflection of the monitored component.

Abstract: Mechanical integrity sensors are provided to detect occurrence of an out-of-tolerance force on a component, such as a circuit board. The mechanical integrity sensor includes a light-blocking container and a light collector disposed within the light-blocking container. The light-blocking container includes a breakable panel. The breakable panel fractures with a force on the breakable panel indicative of the out-of-tolerance force on the component. Fracturing of the breakable panel allows light into the light-blocking container, and the light is collected by the light collector as indicative of the occurrence of the out-of-tolerance force on the component.

Abstract: Controlling a rate of prefetching based on bus bandwidth. A determination is made as to whether a rate of prefetching data from memory into a cache is to be changed. This determination is based on bus utilization, and includes identifying a most utilized bus of a plurality of buses used for the prefetch of data, and monitoring utilization of the most utilized bus. The determination whether the rate of prefetching is to be changed is based on the monitoring. Based on determining that the rate is to be changed, the rate of prefetching is changed.

Abstract: Controlling a rate of prefetching based on bus bandwidth. A determination is made as to whether a rate of prefetching data from memory into a cache is to be changed. This determination is based on bus utilization. Based on determining that the rate is to be changed, the rate of prefetching is changed.

Abstract: Embodiments of the invention include a fracture ring sensor and a method of using the same to detect out of tolerance forces. Aspects of the invention include a product having a defined an out of tolerance force, a fracture ring sensor, and a mounting assembly coupling the fracture ring sensor to the product. The fracture ring sensor is patterned with a conductive trace and is manufactured to break when subjected to a predetermined amount of force. The predetermined amount of force is substantially equal to a percentage of the out of tolerance force of the product.

Abstract: Migration of partially completed instructions. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. The instruction is re-executed on a selected processor to resume forward processing of the instruction. The re-executing includes determining whether model-dependent metadata is to be used by the selected processor in re-executing the instruction. Based on determining the model-dependent metadata is to be used, the model-dependent metadata is used in re-executing the instruction. Based on determining the model-dependent metadata is not to be used, proceeding with re-executing the instruction without using the model-dependent metadata.

Abstract: Storage accesses for merge operations are minimized. A plurality of records of a plurality of input lists are merged. The merging includes determining that an input list of the plurality of input lists has become empty, and checking, based on determining that the input list has become empty, a control specific for the input list. The control is used to determine how to proceed, such as whether to end merging or continue merging.

Abstract: A Sort Lists instruction is provided to perform a sort and/or a merge operation. The instruction is an architected machine instruction of an instruction set architecture and is executed by a general-purpose processor of the computing environment. The executing includes sorting a plurality of input lists to obtain one or more sorted output lists, which are output.