Abstract: Saving and restoring machine state between multiple executions of an instruction. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. Based on determining that the processing of the operation has been interrupted, current metadata of the processor is extracted. The metadata is stored in a location associated with the instruction and used to re-execute the instruction to resume forward processing of the instruction from where it was interrupted.

Abstract: Controlling a rate of prefetching based on bus bandwidth. A determination is made as to whether a rate of prefetching data from memory into a cache is to be changed. This determination is based on bus utilization. Based on determining that the rate is to be changed, the rate of prefetching is changed.

Abstract: A method for implementing a programmable linear feedback shift register instruction, the method includes obtaining, by a processor, the machine instruction for execution, the machine instruction includes a first input operand indicating the current value of a shift register, wherein the shift register includes a data bit for each of a plurality of cells, a second input operand indicating a first sub-set of cells from the plurality of cells, and a logical operation specifier field indicating a logical operation to perform on the first and second input operands. Additionally, executing the machine instruction includes performing the logical operation based on the first input operand, the second input operand, and the logical operation specifier field, and generating an output operand by shifting the current value of the shift register to vacate a cell of the shift register and inserting an output value of the logical operation into the vacated cell of the shift register.

Abstract: A Vector Checksum instruction. Elements from a second operand are added together one-by-one to obtain a first result. The adding includes performing one or more end around carry add operations. The first result is placed in an element of a first operand of the instruction. After each addition of an element, a carry out of a chosen position of the sum, if any, is added to a selected position in an element of the first operand.

Abstract: Systems, methods, and computer-readable media are described for performing data compression in a manner that does not require software to make a call to hardware to close a compressed data block, thereby reducing computational overhead. In response to a request from software to data compression hardware for a data encoding, the hardware may return the data encoding as well as an end-of-block symbol encoding value and bit length. The hardware may load the end-of-block symbol encoding value and bit length into a different area in the returned structure such that the software has direct access to the value. When the software determines that a block should be closed, the software may retrieve the end-of-block symbol and insert it into the block without needing to make a call to hardware. The software may then make a call to the hardware to request a new data encoding for subsequent compressed data blocks.

Abstract: A method, computer program product, and system includes a processor obtaining data including values and generating a value conversion dictionary by applying a parse tree based compression algorithm to the data, where the value conversion dictionary includes dictionary entries that represent the values. The processor obtains a distribution of the values and estimates a likelihood for each based on the distribution. The processor generates a code word to represent each value, a size of each code word is inversely proportional to the likelihood of the word. The processor assigns a rank to each code word, the rank for each represents the likelihood of the value represented by the code word; and based on the rank associated with each code word, the processor reorders each dictionary entry in the value conversion dictionary to associate each dictionary entry with an equivalent rank, the reordered value conversion dictionary comprises an architected dictionary.

Abstract: A computer system includes a plurality of hardware processors, and a hardware accelerator. A first processor among the plurality of processor runs an application that issues a data compression request to compress or decompress a data stream. The hardware accelerator selectively operates in different modes to compresses or decompresses the data stream. Based on a selected mode, the hardware accelerator can utilize a different number of processors among the plurality of hardware to compress or decompress the data stream.

Abstract: Embodiments relate to accessing data in a memory. A method for accessing data in a memory coupled to a processor is provided. The method receives a memory reference instruction for accessing data of a first size at an address in the memory. The method determines an alignment size of the address in the memory. The method accesses the data of the first size in one or more groups of data by accessing each group of data block concurrently. The groups of data have sizes that are multiples of the alignment size.

Abstract: A computer system includes a plurality of hardware processors, and a hardware accelerator. A first processor among the plurality of processor runs an application that issues a data compression request to compress or decompress a data stream. The hardware accelerator selectively operates in different modes to compresses or decompresses the data stream. Based on a selected mode, the hardware accelerator can utilize a different number of processors among the plurality of hardware to compress or decompress the data stream.

Abstract: Increasing the scope of local purges of structures associated with address translation. A hardware thread of a physical core of a machine configuration issues a purge request. A determination is made as to whether the purge request is a local request. Based on the purge request being a local request, entries of a structure associated with address translation are purged on at least multiple hardware threads of a set of hardware threads of the the machine configuration.

Abstract: An embodiment of the invention may include a method, computer program product and system for guided service procedure. The embodiment may include receiving feedback data from one or more of a plurality of sensors. Each of the plurality of sensors may detect a physical condition at a serviceable location within an item of equipment. The item of equipment may be undergoing a service procedure by an equipment servicer. The embodiment may include determining whether the received feedback data from one or more of the plurality of sensors exceeds a threshold value. Based on determining that the threshold value is exceeded, the embodiment may include alerting the equipment servicer during the service procedure.

Abstract: An electro-mechanical fuse is provided and includes a chassis component, an extrusion disposed on a monitored component which is disposable proximate to the chassis component and a sensor. The sensor is mounted to the chassis component. The sensor is mechanically breakable in power-on and power-off conditions by the extrusion as a result of a predefined action of or relative to the monitored component. The sensor electrically signals an occurrence of the mechanical breakage during power-on conditions following mechanical breakage.

Abstract: A system and method for implementing a servicing instruction for a plurality of counters that includes determining a counter set based on the servicing instruction, whether access is authorized to the counter set, and a block of storage in a memory based on the service instruction. In response to the determining that the access is authorized, the system and method extracts the plurality of counters within the counter set in response to the determining that the access is authorized and storing the plurality of counters in the block of storage.

Abstract: A method, computer program product, and system includes a processor obtaining data including values and generating a value conversion dictionary by applying a parse tree based compression algorithm to the data, where the value conversion dictionary includes dictionary entries that represent the values. The processor obtains a distribution of the values and estimates a likelihood for each based on the distribution. The processor generates a code word to represent each value, a size of each code word is inversely proportional to the likelihood of the word. The processor assigns a rank to each code word, the rank for each represents the likelihood of the value represented by the code word; and based on the rank associated with each code word, the processor reorders each dictionary entry in the value conversion dictionary to associate each dictionary entry with an equivalent rank, the reordered value conversion dictionary comprises an architected dictionary.

Abstract: A marking capability is used to provide an indication of whether a block of memory is backing an address translation structure of a control program being managed by a virtual machine manager. By providing the marking, the virtual machine manager may check the indication prior to making paging decisions. With this information, a hint may be provided to the hardware to be used in decisions relating to purging associated address translation structures, such as translation look-aside buffer (TLB) entries.

Abstract: A method for processing an instruction by a processor operationally connected to one or more buses comprises determining the instruction is to access an address of an address space. The address space maps a memory and comprises a range of MMIO addresses. The method determines the address being accessed is within the range of MMIO addresses and translates, based on determining that the address being accessed is within the range of MMIO addresses, the address being accessed using a translation table to a bus identifier identifying one of the buses and a bus address of a bus address space. The bus address space is assigned to the identified bus. The bus address resulting from the translation is assigned to a device accessible via the identified bus. Based on the instruction a request directed to the device is sent via the identified bus to the bus address resulting from the translation.

Abstract: A method for processing an instruction by a processor operationally connected to one or more buses comprises determining the instruction is to access an address of an address space that maps a memory and comprises a range of MMIO addresses. The method determines the address being accessed is within the range of MMIO addresses and generates, based on the determination, a first translation of the address being accessed to a bus identifier identifying one of the buses and a bus address of a bus address space. The bus address resulting from the translation is assigned to a device accessible via the identified bus. The method generates an entry in a translation lookaside buffer. A request directed to the device is sent via the identified bus to the bus address resulting from the translation.

Abstract: Increasing the scope of local purges of structures associated with address translation. A hardware thread of a physical core of a machine configuration issues a purge request. A determination is made as to whether the purge request is a local request. Based on the purge request being a local request, entries of a structure associated with address translation are purged on at least multiple hardware threads of a set of hardware threads of the the machine configuration.

Abstract: An instruction generates a value for use in processing within a computing environment. The instruction obtains a sign control associated with the instruction, and shifts an input value of the instruction in a specified direction by a selected amount to provide a result. The result is placed in a first designated location in a register, and the sign, which is based on the sign control, is placed in a second designated location of the register. The result and the sign provide a signed value to be used in processing within the computing environment.

Abstract: Embodiments are directed to a computer implemented method for executing machine instructions in a central processing unit. The executing includes loading a first operand into a first operand register, and loading a second operand into a second operand register. The executing further includes shifting either the first operand or the second operand to form a shifted operand. The executing further includes adding or subtracting the first operand and the second operand to obtain a sum or a difference, and loading the sum or the difference having a least significant bit into a third register or a memory. The executing further includes performing a probability analysis on least significant bits of the shifted operand or the non-shifted operand, and initiating a rounding operation on the least significant bit of the sum or the difference based at least in part on the probability analysis.