Abstract: Methods and systems disclosed herein relate generally to evaluating resource loads to determine when to transform queues and to specific techniques for transforming at least part of queues so as to correspond to alternative resources.

Abstract: Embodiments relate to processing a request from a user device for access rights for a resource. An access management system can send a request to query a (e.g., cached or authoritative) data store for available access rights. The query may include an exact-match or fuzzy query. A set of access-right results responsive to the query can be identified. The system may transmit a communication to the user device that identifies the set, or a subset thereof. Upon receiving a selection of a result, the system can facilitate assigning access rights corresponding to the identified result to the user. In some instances, a level of precision at which a characteristic of an access-right result is identified and/or whether or how access rights are held depends on a request load.

Abstract: A method for facilitating part fabrication, such as by automated toolpath generation, can include one or more of: receiving a virtual part; modifying the virtual part; and/or determining toolpaths to fabricate the target part. The toolpaths preferably define an ordered series of additive and subtractive toolpaths, more preferably wherein the additive and subtractive toolpaths are interleaved, which can function to achieve high manufacturing efficiency and/or performance. The method can additionally or alternatively include: generating machine instructions based on the toolpaths; fabricating the target part based on the machine instructions; calibrating the fabrication system; and/or any other suitable elements.

Abstract: A method for facilitating part fabrication, such as by automated toolpath generation, can include one or more of: receiving a virtual part; modifying the virtual part; and/or determining toolpaths to fabricate the target part. The toolpaths preferably define an ordered series of additive and subtractive toolpaths, more preferably wherein the additive and subtractive toolpaths are interleaved, which can function to achieve high manufacturing efficiency and/or performance. The method can additionally or alternatively include: generating machine instructions based on the toolpaths; fabricating the target part based on the machine instructions; calibrating the fabrication system; and/or any other suitable elements.

Abstract: A method for facilitating part fabrication, such as by automated toolpath generation, can include one or more of: receiving a virtual part; modifying the virtual part; and/or determining toolpaths to fabricate the target part. The toolpaths preferably define an ordered series of additive and subtractive toolpaths, more preferably wherein the additive and subtractive toolpaths are interleaved, which can function to achieve high manufacturing efficiency and/or performance. The method can additionally or alternatively include: generating machine instructions based on the toolpaths; fabricating the target part based on the machine instructions; calibrating the fabrication system; and/or any other suitable elements.

Abstract: Methods and systems disclosed herein relate generally to evaluating resource loads to determine when to transform queues and to specific techniques for transforming at least part of queues so as to correspond to alternative resources

Abstract: Embodiments relate to processing a request from a user device for access rights for a resource. An access management system can send a request to query a (e.g., cached or authoritative) data store for available access rights. The query may include an exact-match or fuzzy query. A set of access-right results responsive to the query can be identified. The system may transmit a communication to the user device that identifies the set, or a subset thereof. Upon receiving a selection of a result, the system can facilitate assigning access rights corresponding to the identified result to the user. In some instances, a level of precision at which a characteristic of an access-right result is identified and/or whether or how access rights are held depends on a request load.

Abstract: A system comprises: a contactor having a first surface, a second surface, a first hole, a second hole parallel to the first hole, and a third hole parallel to the first hole; a first signal pin held in the first hole of the contactor, extending to at least the second surface of the contactor, and extending to at least the first surface of the contactor; a first short ground pin held in the second hole of the contactor, extending to at least the second surface of the contactor, and extending within the first surface of the contactor; and a ground pin held in the third hole of the contactor, extending to at least the second surface of the contactor, and extending to at least the first surface of the contactor.

Abstract: A controller of a non-volatile memory system may be configured to identify bits of data to be stored in memory elements of non-volatile memory that are identified as unreliable. The controller may be configured to bias at least some of these bits to a predetermined logic value at which the bits are likely to be read from the unreliable memory elements. The controller may do so using a biasing key that the controller generates based on identification of the bits. Subsequently, when the data is read, the controller may assign log likelihood ratio values for the bits to correspond to a percent likelihood of the bits being biased to the predetermined logic value. The bits may also be unbiased using the biasing key.

Abstract: The present invention relates to immunoglobulins that specifically bind CD40L and more in particular to polypeptides, nucleic acids encoding such polypeptides; to methods for preparing such polypeptides; to compositions and in particular to pharmaceutical compositions that comprise such polypeptides, for prophylactic, therapeutic or diagnostic purposes. In particular, the immunoglobulins of the present invention inhibit the activity of CD40L and are safe.

Abstract: A memory system and method for reducing read disturb errors are disclosed. In one embodiment, a memory system is provided comprising a plurality of blocks of memory and a controller. The controller is configured to detect a read disturb error in a block, identify data that caused the read disturb error, and move the data that caused the read disturb error to a block with a higher read endurance. This can be done by assigning read counters to blocks to determine frequently-read data, and storing that data in a separate block until it is less frequently read and will likely not cause additional read disturb errors.

Abstract: A data storage device includes a memory (including a single level cell (SLC) memory portion and a multilevel cell (MLC) memory portion), a plurality of data latches, and routing circuitry coupled to the plurality of data latches. The routing circuitry is configured to cause write data, received from a controller, to be stored at a data latch of the plurality of data latches. The routing circuitry is further configured to cause the write data to be copied from the data latch to a particular portion of the memory based on receiving a program mode command after the write data is stored at the data latch, where the program mode command indicates the particular portion as one of the SLC memory portion or the MLC memory portion.

Abstract: A controller of a non-volatile memory system may be configured to identify bits of data to be stored in memory elements of non-volatile memory that are identified as unreliable. The controller may be configured to bias at least some of these bits to a predetermined logic value at which the bits are likely to be read from the unreliable memory elements. The controller may do so using a biasing key that the controller generates based on identification of the bits. Subsequently, when the data is read, the controller may assign log likelihood ratio values for the bits to correspond to a percent likelihood of the bits being biased to the predetermined logic value. The bits may also be unbiased using the biasing key.

Abstract: A controller of a non-volatile memory system may be configured to identify bits of data to be stored in memory elements of non-volatile memory that are identified as unreliable. The controller may be configured to bias at least some of these bits to a predetermined logic value at which the bits are likely to be read from the unreliable memory elements. The controller may do so using a biasing key that the controller generates based on identification of the bits. Subsequently, when the data is read, the controller may assign log likelihood ratio values for the bits to correspond to a percent likelihood of the bits being biased to the predetermined logic value. The bits may also be unbiased using the biasing key.

Abstract: Systems, apparatuses, and methods for command queue management and configurable memory status in a memory. A memory may include a controller and one or more memory integrated circuit chips, which each include memory arrays. The controller may send commands, such as read or write commands, to the one or more memory integrated circuit chips. The memory integrated circuit chips may maintain a command queue of the commands sent from the controller, thereby relieving the controller from such responsibility. Further, the memory integrated circuit chips may send an indication of an error in executing the commands, thereby relieving the controller from constant polling of the memory integrated circuit chips as to status.

Abstract: A data storage device includes a memory (including a single level cell (SLC) memory portion and a multilevel cell (MLC) memory portion), a plurality of data latches, and routing circuitry coupled to the plurality of data latches. The routing circuitry is configured to cause write data, received from a controller, to be stored at a data latch of the plurality of data latches. The routing circuitry is further configured to cause the write data to be copied from the data latch to a particular portion of the memory based on receiving a program mode command after the write data is stored at the data latch, where the program mode command indicates the particular portion as one of the SLC memory portion or the MLC memory portion.

Abstract: Systems, apparatuses, and methods may be provided that adapt to trim set advancement. Trim set advancement may be a change in trim sets over time. A cell of a semiconductor memory may have a first charge level and be programmed with a first trim set. The cell may be reprogrammed by raising the first charge level to a second charge level that corresponds to the cell programmed with a second trim set.

Abstract: A controller of a non-volatile memory system may be configured to identify bits of data to be stored in memory elements of non-volatile memory that are identified as unreliable. The controller may be configured to bias at least some of these bits to a predetermined logic value at which the bits are likely to be read from the unreliable memory elements. The controller may do so using a biasing key that the controller generates based on identification of the bits. Subsequently, when the data is read, the controller may assign log likelihood ratio values for the bits to correspond to a percent likelihood of the bits being biased to the predetermined logic value. The bits may also be unbiased using the biasing key.

Abstract: A population of memory cells are programmed and an indicator of a first number of the memory cells programmed to a first state is recorded. Subsequently, a first read operation is performed using a first set of read parameters to identify a second number of the memory cells that are read as being in the first state. The difference between the first number and the second number is determined and a second set of read parameters for a second read (reread) is selected accordingly.

Abstract: A system for improving the management and usage of blocks based on intrinsic endurance may be used to improve memory usage for flash memory, such as a memory card. The overall card endurance may be extended by cycling blocks with higher intrinsic endurance over the lowest endurance target of the worst block. This may be accomplished by managing blocks with different intrinsic endurance values internally or by partitioning the blocks with different intrinsic endurance values externally for different usage.