Abstract: A packoff device is disclosed for sealing an annulus within a wellbore, and for bypassing the sealed annulus. The packoff device may include a mandrel having a bore formed axially therethrough and first and second ports extending radially from the bore. A sealing element that extends radially-outwardly from the mandrel may be positioned axially between the first and second ports, and may create a seal within an annulus between the mandrel and a casing, to isolate a portion of the annulus above the sealing element from a portion below the sealing element. A sleeve within the bore may, with the mandrel, form a channel providing fluid communication between the first and second ports. The sleeve may be movable between open and closed states. The first and second ports may be unobstructed by the sleeve in the open state, one or more may be obstructed in the closed state.

Abstract: A semiconductor device may be created using multiple metal layers and a layer including programmable vias that may be used to form various patterns of interconnections among segments of metal layers. The programmable vias may be formed of materials whose resistance is changeable between a high-resistance state and a low-resistance state.

Abstract: A thin plate cutting die has on a front surface a closed cutting edge confining an enclosed area and in a back surface a recess. An air-passage through hole is situated within the enclosed area is opening into the recess, and a positioning indication is established for establishing a correct position of the thin plate cutting die. A cylinder for magnetically holding the thin plate cutting die has at least one longitudinal channel extending longitudinally and internally in the cylinder for transferring air, at least one outlet channel extending from the longitudinal channel and opening into a thin plate die receiving surface, and a positioning indication for establishing a correct position of a thin plate cutting die on the receiving surface.

Abstract: A user logic design for a mask-programmable logic device (“MPLD”) may be designed on a comparable or compatible user-programmable logic device (“UPLD”) and migrated to the MPLD, or may be designed directly on an MPLD. If the design is designed on a UPLD, the constraints of the target MPLD—i.e., differences between the devices—are taken into account so that the migration will be successful. If the design is designed directly on an MPLD, constraints of a comparable compatible UPLD are taken into account if the user indicates that the design will be migrated to the UPLD for testing. This means that when a logic design is intended to be migrated back-and-forth between a UPLD and an MPLD, only the intersection of features can be used. To facilitate migration, fixed mappings between pairs of devices may be created.

Abstract: The present invention relates generally to methods for generating single stranded nucleic acid molecules following enhanced solid phase polynucleotide amplification. The present invention employs an amplification reaction using primers with differential priming properties at particular annealing conditions or an immobilized primer nested between two aqueous phase primers. Thus, by primer design, solid support primer participation is enhanced relative to aqueous phase primers. The subject invention further provides methods for labeling solid matrices with single and double stranded nucleic acid molecules. Kits for generating single stranded nucleic acid molecules and for conducting amplification reactions also form part of the present invention. The present invention further provides amplification systems for the generation of single stranded nucleic acid molecules optionally labelled with a reporter molecule and their use inter alia as labels, primers and probes.

Abstract: A configurable logic array may include a multiplicity of logic components, which may contain customizable look-up tables, and layers of fixed metal segments all of which may be customizable using a single custom via layer. The integrated circuit containing the configurable logic array may also include a multiplicity of customizable register files, customizable RAM blocks; a ROM block with customizable contents; or test logic with customizable test options and configurations to separately test logic and the PLLs.

Abstract: A method for verifying library components and designs on a via customizable ASIC, which may include the process of adding capacitors to model possible via sites of a model of an un-customized portion of or a whole ASIC, and replacing the capacitors with resistors to model where custom vias have been placed on the ASIC to implement a desired component or design. Views of this model may then be generated to verify the functionality of the component or design, and component models for timing, function and via customization may then be generated for the component library.

Abstract: A method is provided for degassing a liquid. One step of the method includes providing a rotating packed bed (RPB) reactor. The RPB reactor includes a rotatable permeable element disposed within a chamber defining an interior region, at least one liquid inlet for infusing the liquid into the interior region, at least one gas outlet for removing a gas from the interior region, and at least one liquid outlet for removing a liquid from the interior region. The rotatable permeable element within the RPB reactor is caused to spin at a tangential velocity, and the liquid is then infused into the at least one liquid inlet at an inlet flow rate. Next, a vacuum is applied to the interior region of the RPB reactor via the at least one gas outlet to generate a liquid substantially free of the gas.

Abstract: A configurable logic array may include a multiplicity of logic components, which may contain customizable look-up tables, and layers of fixed metal segments all of which may be customizable using a single custom via layer. The integrated circuit containing the configurable logic array may also include a multiplicity of customizable register files, customizable RAM blocks; a ROM block with customizable contents; or test logic With customizable test options and configurations to separately test logic and the PLLs.

Abstract: A semiconductor device may be created using multiple metal layers and a layer including programmable vias that may be used to form various patterns of interconnections among segments of metal layers. The programmable vias may be formed of materials whose resistance is changeable between a high-resistance state and a low-resistance state.

Abstract: A user logic design for a mask-programmable logic device (“MPLD”) may be designed on a comparable or compatible user-programmable logic device (“UPLD”) and migrated to the MPLD, or may be designed directly on an MPLD. If the design is designed on a UPLD, the constraints of the target MPLD—i.e., differences between the devices—are taken into account so that the migration will be successful. If the design is designed directly on an MPLD, constraints of a comparable compatible UPLD are taken into account if the user indicates that the design will be migrated to the UPLD for testing. This means that when a logic design is intended to be migrated back-and-forth between a UPLD and an MPLD, only the intersection of features can be used. To facilitate migration, fixed mappings between pairs of devices may be created.

Abstract: A method is provided for degassing a liquid. One step of the method includes providing a rotating packed bed (RPB) reactor. The RPB reactor includes a rotatable permeable element disposed within a chamber defining an interior region, at least one liquid inlet for infusing the liquid into the interior region, at least one gas outlet for removing a gas from the interior region, and at least one liquid outlet for removing a liquid from the interior region. The rotatable permeable element within the RPB reactor is caused to spin at a tangential velocity, and the liquid is then infused into the at least one liquid inlet at an inlet flow rate. Next, a vacuum is applied to the interior region of the RPB reactor via the at least one gas outlet to generate a liquid substantially free of the gas.

Abstract: Prepare a foam structure that includes hollow coalesced foam strands and, optionally, solid coalesced foam strands using an extrusion die block equipped with apertures that promote forming the hollow strands and, optionally, the solid foam strands.

Abstract: Prepare a foam structure that includes hollow coalesced foam strands and, optionally, solid coalesced foam strands using an extrusion die block equipped with apertures that promote forming the hollow strands and, optionally, the solid foam strands.

Abstract: A user logic design for a mask-programmable logic device (“MPLD”) may be designed on a comparable or compatible user-programmable logic device (“UPLD”) and migrated to the MPLD, or may be designed directly on an MPLD. If the design is designed on a UPLD, the constraints of the target MPLD—i.e., differences between the devices—are taken into account so that the migration will be successful. If the design is designed directly on an MPLD, constraints of a comparable compatible UPLD are taken into account if the user indicates that the design will be migrated to the UPLD for testing. This means that when a logic design is intended to be migrated back-and-forth between a UPLD and an MPLD, only the intersection of features can be used. To facilitate migration, fixed mappings between pairs of devices may be created.

Abstract: A method for verifying library components and designs on a via customizable ASIC, which may include the process of adding capacitors to model possible via sites of a model of an un-customized portion of or a whole ASIC, and replacing the capacitors with resistors to model where custom vias have been placed on the ASIC to implement a desired component or design. Views of this model may then be generated to verify the functionality of the component or design, and component models for timing, function and via customization may then be generated for the component library.

Abstract: A method for treating a contaminated fluid includes a step of providing a rotating packed bed (RPB) reactor having a rotatable permeable element disposed within a chamber defining an interior region. The RPB reactor also includes at least one liquid inlet for infusing the contaminated fluid into the interior region, at least one gas inlet for introducing a dose of at least one dissolvable gas into the chamber, at least one gas outlet for removing the at least one dissolvable gas from the interior region, and at least one liquid outlet for removing a fluid from the interior region. The contaminated fluid is infused into the liquid inlet at an inlet flow rate. After causing the rotatable permeable element to spin at a tangential velocity, a dose of the dissolvable gas is then infused into the gas inlet and a treated fluid having a reduced number of contaminants is generated.

Abstract: A mask-programmable logic device that implements a pre-existing circuit design and that includes programmable smart switches is provided. The smart switches are metal terminals that may be programmed to perform configuration-related logic functions of the pre-existing circuit design.

Abstract: A mask-programmable logic device that implements a pre-existing circuit design and that includes programmable smart switches is provided. The smart switches are metal terminals that may be programmed to perform configuration-related logic functions of the pre-existing circuit design.

Abstract: A method for creating a mask-programmed device from a preexisting design of a source device is provided. The method includes creating a netlist from a user defined circuit configuration file, configuring logic resources on the mask-programmed device produce basic logic elements, and generating a custom interconnect based on the netlist that interconnects the configured logic resources to produce the desired logic design.