Abstract: A method for creating a mask-programmed device from a preexisting design of a source device is provided. The method includes creating a netlist from a user defined circuit configuration file, configuring logic resources on the mask-programmed device produce basic logic elements, and generating a custom interconnect based on the netlist that interconnects the configured logic resources to produce the desired logic design.

Abstract: A mask-programmable logic device includes a “dedicated” device-wide distribution network for device-wide signals such as clocks. Distribution networks for secondary clocks and similar signals, as well as for other high-fanout signals, are designed on a custom basis for each user configuration to be implemented by mask programming, using design techniques that are well known in application-specific integrated circuit design. This accomplishes, at the same time, elimination of the need to custom design the device-wide distribution network for each user configuration, preservation of the timing characteristics of a comparable conventional programmable logic device on which the user configuration may be based, reduction of die-size and power requirements as compared to the comparable conventional programmable logic device, and reduction of the average design time necessary to implement a given user configuration.

Abstract: A mask-programmable logic device that includes programmable gate array sites is provided. The gate array sites contain circuit elements that may be programmed to perform certain logic functions that correct problems associated with implementing a preexisting circuit design in mask-programmable device.

Abstract: A user logic design for a mask-programmable logic device (“MPLD”) may be designed on a comparable or compatible user-programmable logic device (“UPLD”) and migrated to the MPLD, or may be designed directly on an MPLD. If the design is designed on a UPLD, the constraints of the target MPLD—i.e., differences between the devices—are taken into account so that the migration will be successful. If the design is designed directly on an MPLD, constraints of a comparable compatible UPLD are taken into account if the user indicates that the design will be migrated to the UPLD for testing. This means that when a logic design is intended to be migrated back-and-forth between a UPLD and an MPLD, only the intersection of features can be used. To facilitate migration, fixed mappings between pairs of devices may be created.

Abstract: A mask-programmable logic device that includes programmable gate array sites is provided. The gate array sites contain circuit elements that may be programmed to perform certain logic functions that correct problems associated with implementing a preexisting circuit design in mask-programmable device.

Abstract: A mask-programmable logic device that includes programmable gate array sites is provided. The gate array sites contain circuit elements that may be programmed to perform certain logic functions that correct problems associated with implementing a preexisting circuit design in mask-programmable device.