Abstract: An integrated circuit output buffer includes a core terminal, a pad terminal, a pad pull-up transistor, a pad pull-down transistor, a pull-up voltage protection transistor, and a selectively conductive pad voltage feedback path. The pad pull-up transistor and the pad pull-down transistor are coupled to the pad terminal and are biased to respectively charge and discharge the pad terminal in response to a data signal received on the core terminal. The pull-up voltage protection transistor is coupled in series between the pad pull-up transistor and the pad terminal and has a control terminal and a well terminal. The selectively conductive pad voltage feedback path is coupled between the pad terminal and the well terminal of the pull-up voltage protection transistor.

Abstract: An integrated circuit oscillator input cell has an oscillator input pad, an oscillator feedback pad, a core terminal, an inverter and an electrostatic discharge protection circuit. The inverter has an inverter input, which is coupled to the oscillator input pad, and an inverter output, which is coupled to the oscillator feedback pad and the core terminal. The electrostatic discharge protection circuit includes a plurality of N-channel protection transistors, which are coupled to the oscillator input pad. The N-channel protection transistors are the only protection transistors that are coupled to the oscillator input pad.

Abstract: An integrated circuit buffer includes a core output terminal, a pad terminal, a pad pull-down transistor, a pad pull-up transistor, a pull-down control circuit and a pull-up control circuit. The pad pull-down transistor and the pad pull-up transistor are coupled to the pad terminal and have pull-up and pull-down control terminals, respectively. The pull-down control circuit is coupled between the core output terminal and the pull-down control terminal. The pull-up control circuit is coupled between the core output terminal and the pull-up control terminal. A pull-up voltage protection transistor is coupled in series between the pad pull-up transistor and the pad terminal and has a control terminal which is coupled to the pad terminal through a voltage feedback circuit.

Abstract: An integrated circuit I/O buffer has an output driver. The output driver includes first, second and third voltage supply terminals and a pad terminal. A pad pull-up transistor is coupled in series between the first voltage supply terminal and the pad terminal and has a pull-up control terminal. A pad pull-down transistor is coupled in series between the second voltage supply terminal and the pad terminal and has a pull-down control terminal. A voltage protection transistor is coupled between the pad terminal and the pad pull-down transistor. The voltage protection transistor has a control terminal and a capacitance between the control terminal and the pad terminal. A resistor is coupled in series between the control terminal of the voltage protection transistor and the third voltage supply terminal and forms a resistor-capacitor (RC) circuit with the capacitance.

Abstract: An integrated circuit having a DC current test function operates at a core supply voltage and interfaces at an input-output (I/O) supply voltage. The I/O supply voltage is greater than the core supply voltage. The integrated circuit includes a buffer, a voltage level shifting circuit and a pull-up circuit. The buffer is coupled between a core terminal and a pad terminal. The pad terminal has a voltage swing which is substantially equal to the I/O supply voltage. The voltage level shifting circuit has a test signal input with a voltage swing substantially equal to the core supply voltage and a test signal output with a voltage swing from the I/O supply voltage to a selected bias voltage. The pull-up circuit is coupled to the pad terminal and has a control terminal coupled to the test signal output.

Abstract: A tri-state input-output (I/O) buffer which includes a core terminal, a pad terminal and an enable terminal. A pad pull-down transistor and pad pull-up transistor are coupled to the pad terminal and have pull-up and pull-down control terminals, respectively. A pull-down control circuit is coupled between the core terminal and the pull-down control terminal. A pull-up control circuit is coupled between the core terminal and the pull-up control terminal. A feedback circuit is coupled between the pad terminal and the pull-up control terminal for sensing a first voltage on the pad terminal and adjusting a second voltage on the pull-up control terminal based on the sensed first voltage to reduce leakage current through the pull-up transistor when an enable signal received on the enable terminal is an inactive state.

Abstract: An arrangement and method for making a gate array architecture locates the well taps at the outer corners of each gate cell. The power buses are also located at the outside of the gate cell as well, enabling sharing of the well taps and the power buses. The location of the well taps at the outside corners of the standard cell reduces the number of transistors in a single repeatable cell from eight transistors to four transistors.

Abstract: An output driver circuit includes first and second supply terminals, first and second complementary data terminals and an output terminal. A pull-up transistor is coupled between the first supply terminal and the output terminal and has a first control terminal. A pull-down transistor is coupled between the second supply terminal and the output terminal and has a second control terminal which is coupled to the second data terminal. A voltage level shifting circuit is coupled between the first complementary data terminal and the first control terminal and is biased between the first supply terminal and a voltage-controlled node. A voltage regulator is coupled to the voltage-controlled node for regulating the node at a selected voltage.

Abstract: An integrated circuit includes a core region and an input-output (I/O) region which has an I/O slot and a voltage supply slot. First and second voltage supply buses and a bias voltage bus extend along the I/O region through the I/O slot and the voltage supply slot. A bias voltage generator is fabricated in the voltage supply slot and is electrically coupled between the first and second voltage supply buses. The bias voltage generator has a bias voltage output which is electrically coupled to the bias voltage bus. A buffer is fabricated in the I/O slot for interfacing with the core region. The buffer includes a bias voltage input which is electrically coupled to the bias voltage bus.

Abstract: An output driver for an integrated circuit. The output driver includes a core data terminal, a pad terminal, a pull-down transistor and a pull-up transistor. The pull-down and pull-up transistors are coupled to the pad terminal and have pull-down and pull-up control terminals, respectively. A first inverter circuit coupled between the core data terminal and the pull-down control terminal. First and second voltage level shifting differential amplifiers are coupled in series between the core data terminal and the pull-up control terminal.