Abstract: Apparatus and methods are provided for operating a non-volatile memory module. In an example, a method can include filling a first plurality of pages of a first non-volatile memory with first data from a first data lane that includes a first volatile memory device, and filling a second plurality of pages of the first non-volatile memory device with second data from a second data lane that includes a second volatile memory device. In certain examples, the first plurality of pages does not include data from the second data lane.

Abstract: Systems and methods of memory operation involving dynamic adjustment of write policy based on performance needs are disclosed. In one embodiment, an exemplary method may comprise monitoring memory performance parameters related to a programming operation being scheduled, selecting a write policy based on the memory performance parameters monitored, executing a memory control process that is configured to switch between a first addressing scheme and a second addressing scheme, and programming a first superpage of the programming operation using the first addressing scheme and programing a second superpage of the programming operation using the second addressing scheme.

Abstract: A factory management and monitoring system includes a processing unit structured to receive data from a plurality of sensors structured to monitor one or more factories or machines included in the factories, to analyze the received data, and to generate a user interface including the received data or information resulting from analysis of the received data, and a display structured to display the user interface.

Abstract: Example electric vehicle charging systems and methods are described. In one example, multiple solar cells are configured to generate energy. A vehicle control system is coupled to the multiple solar cells and determines which of multiple electric vehicles to charge using energy from the multiple solar cells. The vehicle control system determines which electric vehicle to charge based on at least one environmental condition near the multiple solar cells.

Abstract: A variety of applications can include apparatus and/or methods that provide shared parity protection to data in memory devices of a memory system. Parity data of different data streams programmed into different blocks of one or more memory devices can be overlapped and wrapped into slots of a volatile memory arranged as a storage device for the parity data. A parity, map of parity-to-data reflecting the overlapping of the parity data can be maintained in the volatile memory along with the overlapped parity. The parity map can be updated as parity data is generated from further programming of the data streams. The parity contents of the volatile memory, including the parity map, can be transferred to a non-volatile memory in response to a determination of an occurrence of a transfer criterion. The parity contents flushed to the non-volatile memory can be used to allow correct data reconstruction in case of failures in programming.

Abstract: Apparatus and methods are disclosed, including determining whether firmware has been successfully loaded and whether the firmware version is valid and operable, and if the firmware has not been successfully loaded or the firmware is not valid and operable, tracking a number of unsuccessful attempts to load the firmware or an elapsed time for unsuccessful attempts to load the firmware, and entering a memory device into a reduced-power state if either the number of unsuccessful attempts or the elapsed time has reached a programmable threshold.

Abstract: A subcutaneous analyte sensor applicator includes an inserter module and a sensor module. The inserter module includes an applicator housing, a deployment button, and a pre-loaded insertion assembly completely disposed and secured within the button and partially disposed within the applicator housing when the button is in an initial, loaded position on the applicator housing. The insertion assembly includes an assembly housing, and a biasing element and a needle assembly disposed within the assembly housing chamber where the biasing element is in a compressed state. The sensor module includes a sensor lower housing releasably connected to the applicator housing, a sensor upper housing removably retained against the insertion assembly housing and spaced from the sensor lower housing, and an electro-sensor assembly disposed within the sensor upper housing where a sensor is temporarily disposed within a needle of a needle assembly when the applicator system is in the initial pre-loaded position.

Abstract: Apparatus and methods are disclosed, including using a memory controller to monitor at least one parameter related to power level of a host processor of a host device, and dynamically adjusting at least one of a clock frequency and a voltage level of an error-correcting code (ECC) subsystem of the memory controller based on the at least one parameter to control power usage of the host device.

Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

Abstract: A memory device comprises a memory array that includes memory cells and a memory controller operatively coupled to the memory array. The memory controller includes an oscillator circuit, internal memory, a processor core coupled to the oscillator circuit and the internal memory, and configured to load operating firmware during a boot phase of the memory device, voltage detector circuitry configured to detect a decrease in a circuit supply voltage of the memory controller during the boot phase, and logic circuitry configured to halt operation of the oscillator circuit and power down the processor core and the internal memory during the boot phase in a low power mode in response to detecting the decrease in the circuit supply voltage.

Abstract: The disclosed embodiments concern methods, devices, and systems for identifying candidate biomarkers useful for the diagnosis, prognosis, monitoring and screening and/or as targets for the treatment of diseases and conditions in subjects, in particular autoimmune and infectious diseases. The identification of candidate biomarkers is predicated on identifying discriminating peptides present on a peptide array, which can distinguish samples from different subjects having different health conditions by the binding patterns of antibodies present in the samples.

Abstract: Systems and methods are disclosed, including moving host data stored in volatile memory of the storage system to non-volatile memory of the storage system and transitioning a storage system power status of a unidirectional power state signal interface from an active power status to a low power status.

Abstract: A memory device comprises a memory array that includes memory cells and a memory controller operatively coupled to the memory array. The memory controller includes an oscillator circuit, internal memory, a processor core coupled to the oscillator circuit and the internal memory, and configured to load operating firmware during a boot phase of the memory device, voltage detector circuitry configured to detect a decrease in a circuit supply voltage of the memory controller during the boot phase, and logic circuitry configured to halt operation of the oscillator circuit and power down the processor core and the internal memory during the boot phase in a low power mode in response to detecting the decrease in the circuit supply voltage.

Abstract: A body mounting assembly, model vehicle, and method for engaging a model vehicle body to a model vehicle chassis are provided. The body mounting assembly includes a latch assembly. The latch assembly further includes a latch member with a latch engagement surface. The body mounting assembly also includes a retainer assembly. The retainer assembly further includes a retainer engagement surface. The latch assembly is releasably engaged to the retainer assembly when the latch engagement surface and the retainer engagement surface are interlock together. The latch engagement surface and the retainer engagement surface comprise negative engagement angles. A body mount able to be coupled to a model vehicle body includes one of the latch assembly or the retainer assembly and a chassis mount able to be coupled to the model vehicle chassis includes the other corresponding retainer assembly or the latch assembly corresponding to the body mount.

Abstract: A model vehicle with body mount components are provided. A tongue member attached to a model vehicle body with a first and second tongue member is configured to engage a first securing member attached to a model vehicle chassis. A top surface of the second tongue member draws the model vehicle body towards the model vehicle chassis when the second tongue member engages the first securing member. A lever member with a lever handle, jaw clamp, and a lever pivot is configured to pivot between an engage and an unengaged position. The jaw clamp engages with a second securing member in the engaged position. The lever member further contains a retaining mechanism that is configured to rotate between a retained and unretained position. The retaining mechanism inhibits the lever handle from moving from the engaged to the unengaged position when the retaining mechanism is in the retained position.