Abstract: A subcutaneous analyte sensor applicator includes an inserter module and a sensor module. The inserter module includes an applicator housing, a deployment button, and a pre-loaded insertion assembly completely disposed and secured within the button and partially disposed within the applicator housing when the button is in an initial, loaded position on the applicator housing. The insertion assembly includes an assembly housing, and a biasing element and a needle assembly disposed within the assembly housing chamber where the biasing element is in a compressed state. The sensor module includes a sensor lower housing releasably connected to the applicator housing, a sensor upper housing removably retained against the insertion assembly housing and spaced from the sensor lower housing, and an electro-sensor assembly disposed within the sensor upper housing where a sensor is temporarily disposed within a needle of a needle assembly when the applicator system is in the initial pre-loaded position.

Abstract: Apparatus and methods are disclosed, including using a memory controller to monitor at least one parameter related to power level of a host processor of a host device, and dynamically adjusting at least one of a clock frequency and a voltage level of an error-correcting code (ECC) subsystem of the memory controller based on the at least one parameter to control power usage of the host device.

Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

Abstract: A memory device comprises a memory array that includes memory cells and a memory controller operatively coupled to the memory array. The memory controller includes an oscillator circuit, internal memory, a processor core coupled to the oscillator circuit and the internal memory, and configured to load operating firmware during a boot phase of the memory device, voltage detector circuitry configured to detect a decrease in a circuit supply voltage of the memory controller during the boot phase, and logic circuitry configured to halt operation of the oscillator circuit and power down the processor core and the internal memory during the boot phase in a low power mode in response to detecting the decrease in the circuit supply voltage.

Abstract: The disclosed embodiments concern methods, devices, and systems for identifying candidate biomarkers useful for the diagnosis, prognosis, monitoring and screening and/or as targets for the treatment of diseases and conditions in subjects, in particular autoimmune and infectious diseases. The identification of candidate biomarkers is predicated on identifying discriminating peptides present on a peptide array, which can distinguish samples from different subjects having different health conditions by the binding patterns of antibodies present in the samples.

Abstract: A memory device comprises a memory array that includes memory cells and a memory controller operatively coupled to the memory array. The memory controller includes an oscillator circuit, internal memory, a processor core coupled to the oscillator circuit and the internal memory, and configured to load operating firmware during a boot phase of the memory device, voltage detector circuitry configured to detect a decrease in a circuit supply voltage of the memory controller during the boot phase, and logic circuitry configured to halt operation of the oscillator circuit and power down the processor core and the internal memory during the boot phase in a low power mode in response to detecting the decrease in the circuit supply voltage.

Abstract: Systems and methods are disclosed, including moving host data stored in volatile memory of the storage system to non-volatile memory of the storage system and transitioning a storage system power status of a unidirectional power state signal interface from an active power status to a low power status.

Abstract: A body mounting assembly, model vehicle, and method for engaging a model vehicle body to a model vehicle chassis are provided. The body mounting assembly includes a latch assembly. The latch assembly further includes a latch member with a latch engagement surface. The body mounting assembly also includes a retainer assembly. The retainer assembly further includes a retainer engagement surface. The latch assembly is releasably engaged to the retainer assembly when the latch engagement surface and the retainer engagement surface are interlock together. The latch engagement surface and the retainer engagement surface comprise negative engagement angles. A body mount able to be coupled to a model vehicle body includes one of the latch assembly or the retainer assembly and a chassis mount able to be coupled to the model vehicle chassis includes the other corresponding retainer assembly or the latch assembly corresponding to the body mount.

Abstract: A model vehicle with body mount components are provided. A tongue member attached to a model vehicle body with a first and second tongue member is configured to engage a first securing member attached to a model vehicle chassis. A top surface of the second tongue member draws the model vehicle body towards the model vehicle chassis when the second tongue member engages the first securing member. A lever member with a lever handle, jaw clamp, and a lever pivot is configured to pivot between an engage and an unengaged position. The jaw clamp engages with a second securing member in the engaged position. The lever member further contains a retaining mechanism that is configured to rotate between a retained and unretained position. The retaining mechanism inhibits the lever handle from moving from the engaged to the unengaged position when the retaining mechanism is in the retained position.

Abstract: A disposable test cartridge and method for a point-of-care analyzer includes a cartridge body having a plurality of chambers where each of the plurality of chambers has an opening at a top of the cartridge body, a cartridge cover connected to the cartridge body where the cartridge cover has a capillary-receiving aperture, a capillary wiper disposed within the capillary-receiving aperture where the capillary-receiving aperture is aligned with one of the plurality of chambers of the cartridge body, and a capillary element removably insertable into the cartridge cover where the capillary element has a capillary tube that extends into the capillary-receiving aperture and through the capillary wiper where a tip portion of the capillary tube extends into the cartridge body.

Abstract: A variety of applications can include a memory device having a memory die designed to control a power budget for a cache and a memory array of the memory die. A first flag received from a data path identifies a start of a cache operation on the data and a second flag from the data path identifies an end of the cache operation. A controller for peak power management can be implemented to control the power budget based on determination of usage of current associated with the cache from the first and second flags. In various embodiments, the controller can be operable to feedback a signal to a memory controller external to the memory die to adjust an operating speed of an interface from the memory controller to the memory die. Additional devices, systems, and methods are discussed.

Abstract: An alpha ion emitter apparatus, including a circuit, a fluid duct including one or more apertures, and a rail electrically connected to the circuit and operatively arranged to hold an alpha ionization material that emits alpha particles, the alpha particles creating alpha ions, wherein the circuit is operatively arranged to apply an output signal to at least one of the fluid duct and the rail.

Abstract: Systems and methods are disclosed comprising receiving a request for a descriptor of a storage system, sending the descriptor to the host including an indication that a component of the storage device is in a restricted operation mode, wherein the host device utilizes the indication to determine a boot mode of the host device.

Abstract: Provisioning industrial internet of things (IIOT) devices arranged for deployment in disparate geographic locations includes grouping a subset of IIOT devices into a batch. Each IIOT device stores a system-wide unique identifier (SWUI) and first communication information that identifies a global computing server. The method includes recording with a first input system the SWUI of each IIOT device in the batch, generating a batch identifier, associating the batch identifier with the batch of IIOT devices or each IIOT device in the batch, and associating the batch identifier with customer information. The customer information is associated with second communication information, which identifies a customer-based computing server. The method includes receiving, at the global computing server, incoming communications from a selected IIOT device, and based on the SWUI, and retrieving the batch identifier.

Abstract: In various embodiments, a technique can be provided to address debug efficiency for failures found on an operational system. The approach can make use of an existing pin on a memory device with added logic to respond to a trigger signal structured different from a signal that is normally sent to the existing pin on the memory device such that the memory device performs a normal or routine function of the memory device in response to the signal. In response to detecting one or more error conditions associated with the memory device, a system that interfaces with the memory device can generate the trigger signal to the memory device. In response to receiving the trigger signal, the memory device can dump an error log of the memory device to a memory component in the memory device. The error log can later be retrieved from the memory component for failure analysis.

Abstract: Example electric vehicle charging systems and methods are described. In one implementation, an electric vehicle charging system includes multiple solar cells and a power manager coupled to the multiple solar cells. The power manager receives power signals from each of the solar cells and generates an output signal based on at least a portion of the received power signals. The output signal has an associated voltage and/or current that is within an acceptable operating range for charging an electric vehicle.

Abstract: A support adapted for mounting to wire shelving units, particularly a support adapted to be securely coupled and repositioned on upper and lower horizontally-extending wire members located at the front of wire shelving units. The support does not interfere with use of a shelving unit including the storage of items on the shelving unit or handing items under the shelving unit.