Abstract: A light emitting device is provided. The light emitting device comprises an active layer comprising a plurality of well layers and a plurality of barrier layers. The bather layers comprise a first barrier layer having a first band gap which is the nearest to the second conductive type semiconductor layer, a second barrier layer adjacent to the first barrier, and a third barrier layer between the second bather layer and the first conductive type semiconductor layer. The well layers comprise a first well layer having a third band gap different from the first band gap between the first and second bather layers, and a second well layer between the second barrier layer and the third barrier layer, the second well layer having a second band gap. The first well layer has a thickness thinner than that of the second well layer.

Abstract: A layout method of junction diodes for preventing damage caused by plasma charge includes forming an active layer to form a plurality of active regions in a unit layout pattern; forming a gate layer to form a plurality of gate regions on the active regions; forming a first conductive type doping region in at least one of the plurality of active regions within a well layer where a second conductive type well region is formed to form a first conductive type active region; forming a second conductive type doping region in at least one of the plurality of active regions outside of the second conductive type well region to form a second conductive type active region; and forming a second conductive type doping region connected with the gate regions to form a junction diode in at least one active region between the first and second conductive type active regions.

Abstract: Provided is a layout method of junction diodes for preventing damage caused by plasma charge. The layout method includes operations of forming an active layer so as to form a plurality of active regions in a unit layout pattern; forming a gate layer so as to form a plurality of gate regions on the active regions; forming a first conductive type doping region in at least one of the plurality of active regions within a well layer where a second conductive type well region is formed so as to form a first conductive type active region; forming a second conductive type doping region in at least one of the plurality of active regions outside of the second conductive type well region so as to form a second conductive type active region; and forming a second conductive type doping region connected with the gate regions so as to form a junction diode in at least one active region between the first and second conductive type active regions.

Abstract: A semiconductor memory device includes a sub memory cell array region having memory cells each connected between word lines extending in a first direction and bit lines extending in a second direction that is orthogonal to the first direction of extension of the word lines and a sub word line driver region disposed at a side of the sub memory cell array region in the first direction and including sub word line drivers that activate the word lines. A sensing region is disposed at a side of the sub memory cell array region in the second direction and including an equalizer that precharges the bit line in response to a signal transferred through a drive signal line and at least one first control signal driver that activates an inverted control signal line in response to a signal transferred through a control signal line. A conjunction region disposed at an intersection between the sub word line driver region and the sensing region, in which the inverted control signal line is connected to the drive signal line.

Abstract: A light emitting device includes an active layer having quantum walls and quantum wells, a first conductive type semiconductor layer on one side of the active layer, a second conductive type semiconductor layer on the other side of the active layer, and an interfacial layer arranged between the active layer and the first conductive type semiconductor layer or between the active layer and the second conductive type semiconductor layer, wherein the interfacial layer includes barrier layers and basal layers provided between the barrier layers, wherein an energy bandgap of each of the barrier layers increases from the first conductive type semiconductor layer or the second conductive type semiconductor layer to an active layer direction linearly, and greatest energy bandgaps of the barrier layers are different from one another.

Abstract: Provided are a light emitting device, a light emitting device package, and a lighting system. The light emitting device includes a substrate, a light emitting structure comprising a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer, the light emitting structure being disposed on the substrate, a nonmetal pattern disposed between the substrate and the active layer, the nonmetal pattern being spaced from the substrate, and an air gap disposed on a side surface of the nonmetal pattern.

Abstract: Provided are a light emitting device and a light emitting device package including the same. The light emitting device comprises a first conductive type semiconductor layer, an active layer comprising a plurality of quantum well layers and a plurality of barrier layers, which are alternately laminated on the first conductive type semiconductor layer, and a second conductive type semiconductor layer on the active layer. The plurality of barrier layers comprise a plurality of first barrier layers comprising a conductive type dopant, and the conductive type dopant doped into the plurality of first barrier layers have different doping concentrations for each layer.

Abstract: A data line layout includes column selection lines arranged in a first direction at a layer on a memory cell array region, and data lines arranged in the first direction at the layer, the data lines being connected between I/O sense amplifiers and I/O pads.

Abstract: A nitride semiconductor device is provided. In the device, first and second conductivity type nitride layers are formed. An active layer is formed between the first and second conductivity type nitride layers. The active layer includes at least one quantum barrier layer and at least one quantum well layer. Also, a current spreading layer is interposed between the first conductivity type nitride layer and the active layer. The current spreading layer has an In content greater than the quantum well layer of the active layer.

Abstract: A semiconductor memory device includes a sub memory cell array region having memory cells each connected between word lines extending in a first direction and bit lines extending in a second direction that is orthogonal to the first direction of extension of the word lines and a sub word line driver region disposed at a side of the sub memory cell array region in the first direction and including sub word line drivers that activate the word lines. A sensing region is disposed at a side of the sub memory cell array region in the second direction and including an equalizer that precharges the bit line in response to a signal transferred through a drive signal line and at least one first control signal driver that activates an inverted control signal line in response to a signal transferred through a control signal line. A conjunction region disposed at an intersection between the sub word line driver region and the sensing region, in which the inverted control signal line is connected to the drive signal line.

Abstract: Provided is a layout method of junction diodes for preventing damage caused by plasma charge. The layout method includes operations of forming an active layer so as to form a plurality of active regions in a unit layout pattern; forming a gate layer so as to form a plurality of gate regions on the active regions; forming a first conductive type doping region in at least one of the plurality of active regions within a well layer where a second conductive type well region is formed so as to form a first conductive type active region; forming a second conductive type doping region in at least one of the plurality of active regions outside of the second conductive type well region so as to form a second conductive type active region; and forming a second conductive type doping region connected with the gate regions so as to form a junction diode in at least one active region between the first and second conductive type active regions.

Abstract: The present invention provides a group III-nitride light emitting device improved in operating voltage and electrostatic discharge characteristics. The group III-nitride light emitting device comprises a lower n-type clad layer, a current spreading layer, an upper n-type clad layer, an active layer and an p-type clad layer formed in their order on a substrate. The current spreading layer includes a SiC layer.

Abstract: Provided is a nitride semiconductor light emitting device having enhanced output power and resistance to electrostatic discharge. The light emitting device comprises an n-side contact layer formed on a substrate, a current diffusion layer formed on the n-side contact layer, an active layer formed on the current diffusion layer, and a p-type clad layer formed on the active layer. The current diffusion layer is formed by alternately stacking at least one first InAlGaN layer having a higher electron concentration than that of the n-side contact layer and at least one second InAlGaN layer having a lower electron concentration than that of the n-side contact layer.

Abstract: A layout structure of a bit line sense amplifier is provided.

Abstract: A layout structure of a bit line sense amplifier is provided.

Abstract: A semiconductor memory device having a hierarchical I/O line structure is provided. The semiconductor memory array includes a memory cell array which is divided into a plurality of sub-arrays by sub-word line driver areas and bit line sense amplifier areas; local input/output (I/O) lines which are arranged in the bit line sense amplifier areas; and global I/O lines which are arranged in the sub-word line driver areas, wherein at least one end of each of the local I/O lines is formed in a bit line sense amplifier area. The semiconductor memory device may also have a dummy bit line sense amplifier area capable of dividing local I/O lines in a bit line sense amplifier area, and can reduce the number of sub-word line driver areas such that the chip size can be reduced.

Abstract: A memory device having a memory core, a local equalizer, and a local-global multiplexer. The memory core is connected to local input/output lines and global input/output lines. The local equalizer is configured to precharge the local input/output lines. The global multiplexer is configured to alternately connect and disconnect the local input/output lines with the global input/output lines. The local equalizer is in a same layer of the memory device as the local-global multiplexer.

Abstract: A memory device having a memory core, a local equalizer, and a local-global multiplexer. The memory core is connected to local input/output lines and global input/output lines. The local equalizer is configured to precharge the local input/output lines. The global multiplexer is configured to alternately connect and disconnect the local input/output lines with the global input/output lines. The local equalizer is in a same layer of the memory device as the local-global multiplexer.

Abstract: A semiconductor memory device having a hierarchical I/O line structure is provided. The semiconductor memory array includes a memory cell array which is divided into a plurality of sub-arrays by sub-word line driver areas and bit line sense amplifier areas; local input/output (I/O) lines which are arranged in the bit line sense amplifier areas; and global I/O lines which are arranged in the sub-word line driver areas, wherein at least one end of each of the local I/O lines is formed in a bit line sense amplifier area. The semiconductor memory device may also have a dummy bit line sense amplifier area capable of dividing local I/O lines in a bit line sense amplifier area, and can reduce the number of sub-word line driver areas such that the chip size can be reduced.

Abstract: The present invention discloses a semiconductor memory device and a method of signal line arrangement. The semiconductor memory device comprises a plurality of memory cell array blocks, a number of pairs of local data input/output lines arranged along a longitudinal direction in each of the memory cell array blocks, multiple column selecting signal lines arranged along an orthogonal direction, and a number of twisted pairs of global data input/output lines arranged adjacent to and along the same direction as the column selecting signal line. Therefore, reducing signal coupling among the column selecting signal line and the pair of global data input/output lines.