Abstract: The present invention discloses a semiconductor memory device and a method of signal line arrangement. The semiconductor memory device comprises a plurality of memory cell array blocks, a number of pairs of local data input/output lines arranged along a longitudinal direction in each of the memory cell array blocks, multiple column selecting signal lines arranged along an orthogonal direction, and a number of twisted pairs of global data input/output lines arranged adjacent to and along the same direction as the column selecting signal line. Therefore, reducing signal coupling among the column selecting signal line and the pair of global data input/output lines.

Abstract: A memory device having reduced power consumption by minimizing the operation of circuits utilized in reading and writing data, and a data reading and writing method of the memory device, are provided. In the memory device, upon data reading, an input and output sense amplifier amplifies data which is read from a memory cell and transferred to an input and output line, and transfers the resultant data to a data output line. Upon data writing, a writing driver receives write data via a data input line and transfers the received write data to the input and output line. Each of the input and output sense amplifier and the writing driver operates only when previously-read or -written data is different from current data to be read or written.

Abstract: A memory test control circuit in an MML integrated circuit is connected to a first pad which receives memory control signals to control first and second memories of the MML circuit. The memory test control circuit is also connected to a second pad which receives memory data signals for the first and second memories. The memory test control circuit is also connected to the logic block and to the first and second memories. The memory test control circuit transmits the memory control signals and the memory data signals to the first and second memories when the first and second memories are tested and transmits the memory control signals and the memory data signals to the logic block during normal operation of the MML integrated circuit. Accordingly, the memory test control circuit allows pass-through of memory data and control signals directly to the memory blocks during test mode, and provides the memory data and control signals to the logic block during normal operations.

Abstract: A method of controlling the buffering of output data by synchronizing with an external system clock, including the steps of generating an internal clock pulse, transferring data from a chip to a pair of data output lines in response to the internal clock pulse, generating an output mode control signal in synchronism with the internal clock pulse, gating the output mode control signal from the first edge of the internal clock pulse to the first edge of the next internal clock pulse to produce an output control signal, and driving data output to an output pad in response to the output control signal is disclosed.