Abstract: A gate driving circuit includes: a pull-up controller applying a carry signal of one of previous stages to a first node in response to the carry signal of the one of the previous stages; a pull-up part outputting a clock signal as an N-th gate output signal; a carry part outputting the clock signal as an N-th carry signal; a first pull-down part pulling down the signal at the first node to a second off voltage; a second pull-down part pulling down the N-th gate output signal to a first off voltage; an inverting part generating an inverting signal based on the clock signal and the second off voltage to output the inverting signal to an inverting node; and a reset part outputting a reset signal to the inverting node.

Abstract: There is provided a display device including a display including a first pixel connected to a first data line and a second pixel connected to a second data line, a data signal generator configured to generate an output signal, and a signal divider configured to divide the output signal, to generate a first data signal and a second data signal, and to apply the first data signal and the second data signal to the first data line and the second data line, respectively, wherein the data signal generator is configured to generate the output signal based on a coupling effect of a first parasitic capacitor formed between the first data line and the second data line and a coupling effect of a parasitic capacitor of a data line formed by the first data line and second data line.

Abstract: A gate driver includes a plurality of stage circuits to output a clock signal from the outside as gate signals. A jth stage circuit includes an input unit to charge a first node at an initial voltage when a first input signal is input to a first input terminal, a buffer unit to output the clock signal as a gate signal to an output terminal when the initial voltage is supplied to the first node, a holding unit to maintain the first node at a reset power source level when the clock signal is supplied to the holding unit, and an inverter unit to supply the clock signal or the reset power source to the holding unit. The input unit maintains the first node at a second input signal input voltage to a second input terminal when a third input signal is input to a third input terminal.

Abstract: Stainless steel for a fuel cell separator plate and a manufacturing method therefor are disclosed. The stainless steel for a fuel cell separator plate, according to one embodiment of the present invention, comprises: a stainless base material; and a passive film formed on the stainless base material, wherein a Cr/Fe atomic weight ratio in a 1 nm or less thickness region of the stainless base material, which is adjacent to an interface between the stainless and the passive film, is 0.45 or more. Therefore, by modifying the surface of the stainless steel for a fuel cell separator plate, a low interface contact resistance and a good corrosion resistance can be obtained, and a separate additional process such as precious metal coating can be removed, such that manufacturing costs are reduced and productivity can be improved.

Abstract: A film touch sensor in which a conductive pattern layer and a separation layer are sequentially disposed, and a base film is disposed on at least one surface of the conductive pattern layer and the separation layer, includes a capping layer which is disposed between the separation layer and the conductive pattern layer and includes SiOxNy (0?x?4, y=4?x), thereby it is possible to improve visibility of an image and reduce a resistance of the conductive pattern layer, and a method for fabricating the same.

Abstract: A display device including a first base substrate, gate lines disposed on the first base substrate and extending in a first direction, parasitic capacitance electrodes coupled to the gate lines, data lines extending in a second direction crossing the first direction, transistors, each coupled to one of the gate lines and coupled to one of the data lines, and pixels sequentially arranged in the first direction, each of the pixels coupled to a corresponding one of the transistors, respectively, in which each of the transistors includes a gate electrode, a source electrode, and a drain electrode, and wherein widths of the parasitic capacitance electrodes in adjacent pixels measured along the first direction are different from each other.

Abstract: A system for cleaning a fuel cap valve of a vehicle, may include a fuel cap having an air breather passage and a negative-pressure valve body configured for opening or closing the air breather passage; a canister for collecting evaporated gas inside a fuel tank to supply the evaporated gas into an engine intake system; and a negative-pressure control mechanism for controlling an engine negative pressure, which is applied from the engine intake system to the negative-pressure valve body of the fuel cap through the canister and the fuel tank, to reach a predetermined level or more, or for controlling the engine negative pressure at a repetition interval, in a fuel cap cleaning mode for cleaning the negative-pressure valve body of the fuel cap.

Abstract: A gate circuit according to an exemplary embodiment of the present inventive concept comprises a plurality of stages, each receiving a clock signal and outputting a gate signal and a carry signal. One of the plurality of stages includes a first transistor of which a first terminal and a control terminal are connected to each other and a carry signal of a stage before previous stage is input to the first terminal and the control terminal and a second transistor of which a gate signal of the previous stage is input to a first terminal, a control terminal is connected with a second terminal of the first transistor, and an output terminal is connected to a first node.

Abstract: A display device includes a display area including a gate line and a data line and a gate driver connected to an end of the gate line, the gate driver including at least one stages integrated on a substrate configured to output a gate voltage, in which the stage includes an inverter unit and an output unit, in which the output unit includes a first transistor and a first capacitor. The first transistor includes an input terminal applied with a clock signal, a control terminal connected to the node Q, and an output terminal connected to a gate voltage output terminal through which the gate voltage is output. An inverter voltage output from the inverter is lower than the low voltage of the gate voltage output by the output unit.

Abstract: A demultiplexer includes: a first transistor connected between a data input terminal and a first output terminal; a second transistor connected between the data input terminal and a second output terminal; and a first pre-charge circuit connected to a gate electrode of the first transistor, the first pre-charge circuit including: a third transistor and a first diode connected between a first clock input terminal and the gate electrode of the first transistor in parallel; and a first capacitor connected between a second clock input terminal and the gate electrode of the first transistor.

Abstract: A display device includes: a display unit including a plurality of pixels, each of the pixels including: an OLED; and a driving transistor to supply current to an anode of the OLED according to a voltage applied to a gate of the driving transistor and a power supply voltage; a scan driver to supply scan signals to the pixels; an initialization driver to supply initializing signals to the pixels; a data driver to supply data signals to the pixels; light emission drivers to supply first and second light emission signals to the pixels; and a power supply to supply the power supply voltage and an initialization voltage to the pixels, wherein the initialization voltage is supplied to the anode during a first period, and the power supply voltage corresponding to a threshold voltage of the driving transistor is supplied to the gate during a first sub-period of the first period.

Abstract: A gate driving circuit including: a plurality of stages outputting signals to gate lines, the stages includes a first transistor of which one end and a control terminal are connected, one end and the control terminal are connected with a first input terminal, and the other end is connected to a second node, a second transistor including a control terminal connected to a first node, connected with a clock input terminal, and the other end connected to a first output terminal, a first capacitor of which one end is connected to the first node, the other end is connected to the other end of the second transistor and the first output terminal, and a third transistor of which one end is connected to the other end of the first transistor, the other end is connected with the first node, and a control terminal is connected to a third node.

Abstract: Provided is a ferritic stainless steel including, as a ferritic stainless steel used in a separator for a fuel cell, a base material including, in weight %, C: 0.003% to 0.012%, N: 0.003% to 0.015%, Si: 0.05% to 0.15%, Mn: 0.3% to 0.8%, Cr: 20% to 24%, Mo; 0.1% to 0.4%, Nb: 0.1% to 0.7%, Ti: 0.03% to 0.1%, and the remainder being Fe and inevitable impurities. A first scale layer including chromium oxide is formed on a surface of the base material, and a second scale layer including chromium oxide and manganese oxide is formed on a surface of the first scale layer. A silicon content included in each of the first scale layer and the second scale layer is 0.2 weight % or less, and the following formula is satisfied: Nb+Mn?8Si where Nb, Mn and Si are weight % amounts of corresponding components, respectively.

Abstract: Provided is an austenitic stainless steel for a fuel cell including, in weight %, C: 0.05% to 0.09%, Si: 0.5% or less (0 excluded), Mn: 2.5% to 5.0%, Cr: 21% to 23%, Ni: 10% to 12%, Nb: 0.2% to 0.7%, N: 0.25% or less (0 excluded), Al: 0.2% or less (0 excluded), S: 0.003% or less (0 excluded), B: 0.01% or less (0 excluded), the remainder being Fe and unavoidable impurities.

Abstract: A stage circuit includes a first driver, a second driver, a first output unit, a second output unit and a controller. The first driver controls voltages of first and second nodes, according to a first power source, a third power source, a start signal or a carry signal of a previous stage input to a first input terminal, and a clock signal supplied to a second input terminal. The second driver controls voltages of third and fourth nodes, according to voltages of the first power source, the third power source, the first input terminal and the first and second nodes. The first output unit outputs a carry signal to a first output terminal, according to voltages of the first power source, the second input terminal and the third and fourth nodes. The second output unit outputs a scan signal to a second output terminal, according to voltages of the second power source, the second input terminal and the third and fourth nodes. The controller is electrically coupled to the first output terminal and the second driver.

Abstract: The present invention provides a touch sensor panel and a fabrication method thereof, in which metal wires for forming a metal mesh are subject to patterning to have symmetrical components being in correlation with each other on the basis of x and y axes, thereby improving visibility. In the touch sensor panel and the fabrication method thereof, the metal wires consist of continuous unit wires in which a unit wire and another unit wire crossing with the unit wire have symmetrical components being in correlation with each other and the size of the symmetrical components is determined based on the line width of the unit wires.

Abstract: Provided is a ferrite-based stainless steel having superior moldability when molding a fuel cell divider sheet from a material by controlling yield point elongation in accordance with alloy components. The ferrite-based stainless steel comprises, in weight percentages: no more than 0.02% of C; no more than 0.02% of N; no more than 0.4% of Si; no more than 0.2% of Mn; no more than 0.04% of P; no more than 0.02% of S; 25.0-32.0% of Cr; 0-1.0% of Cu; no more than 0.8% of Ni; no more than 0.01-0.5% of Ti; no more than 0.01-0.5% of Nb; no more than 0.01-1.5% of V; and residual Fe and inevitable elements, wherein the content of Ti, Nb, V, C, and N in terms of weight % of steel uses Formula (1) to render a yield point elongation of the material of no more than 1.1%, and wherein a steel material has superior moldability. 9.1C?1.76V+5.37(C+N)/Ti?1.22Nb?0.7.

Abstract: A coupling compensator for a display panel and a display device including the coupling compensator are disclosed. In one aspect, the coupling compensator includes a memory configured to receive grayscale data and store the grayscale data and a first data converter configured to convert the grayscale data to a plurality of grayscale data voltages including first and second grayscale data voltages. The compensator also includes a coupling voltage calculator configured to calculate a line coupling voltage generated on a data line based on the difference between the first grayscale data voltage corresponding to the grayscale data provided to a first group of the pixels in an (N?1)th row and the second grayscale data voltage corresponding to the grayscale data provided to a first group of the pixels in an Nth row, where the N is an integer equal to or greater than 2.

Abstract: A stage includes a first transistor including an input terminal to which a clock signal is applied and a control terminal connected to a first node; a first capacitor including terminals respectively connected to the first node and an output terminal of the first transistor; a second transistor including an input terminal connected to the output terminal of the first transistor, a control terminal connected to a second node, and an output terminal to which a low voltage is applied; a third transistor including an output terminal connected to the second node, a control terminal connected to the first node, and an input terminal to which the low voltage is applied; and a fourth transistor including an input terminal connected to the first node and an output terminal to which the low voltage is applied, wherein the fourth transistor is switched according to an output signal of a next stage.