Abstract: A gate driver includes a plurality of stages connected to each other in a cascade manner, where each of the stages includes an input unit which connects a first input terminal and a first node and includes a first input transistor and a second input transistor, where an output terminal of the first input transistor and an input terminal of the second input transistor are connected to a second node, and the input unit further includes a storage capacitor which connects the first input terminal and the second node.

Abstract: A gate driving circuit includes: a pull-up controller applying a carry signal of one of previous stages to a first node in response to the carry signal of the one of the previous stages; a pull-up part outputting a clock signal as an N-th gate output signal; a carry part outputting the clock signal as an N-th carry signal; a first pull-down part pulling down the signal at the first node to a second off voltage; a second pull-down part pulling down the N-th gate output signal to a first off voltage; an inverting part generating an inverting signal based on the clock signal and the second off voltage to output the inverting signal to an inverting node; and a reset part outputting a reset signal to the inverting node.

Abstract: A display device includes a display area including a gate line and a data line and a gate driver connected to an end of the gate line, the gate driver including at least one stages integrated on a substrate configured to output a gate voltage, in which the stage includes an inverter unit and an output unit, in which the output unit includes a first transistor and a first capacitor. The first transistor includes an input terminal applied with a clock signal, a control terminal connected to the node Q, and an output terminal connected to a gate voltage output terminal through which the gate voltage is output. An inverter voltage output from the inverter is lower than the low voltage of the gate voltage output by the output unit.

Abstract: A scan driver includes a plurality of stages to receive one or more clock signals, each of the plurality of stages to supply a carry signal to a corresponding first output terminal and to supply a scan signal to a corresponding second output terminal, corresponding to a voltage of a corresponding first node, and each of the plurality of stages including a reset unit, the reset unit to initialize the first node, the first output terminal, and the second output terminal, corresponding to a gate start pulse supplied to a corresponding reset input terminal.

Abstract: A stage circuit includes a first driver, a second driver, a first output unit, a second output unit and a controller. The first driver controls voltages of first and second nodes, according to a first power source, a third power source, a start signal or a carry signal of a previous stage input to a first input terminal, and a clock signal supplied to a second input terminal. The second driver controls voltages of third and fourth nodes, according to voltages of the first power source, the third power source, the first input terminal and the first and second nodes. The first output unit outputs a carry signal to a first output terminal, according to voltages of the first power source, the second input terminal and the third and fourth nodes. The second output unit outputs a scan signal to a second output terminal, according to voltages of the second power source, the second input terminal and the third and fourth nodes. The controller is electrically coupled to the first output terminal and the second driver.

Abstract: A stage circuit includes an output part configured to supply a carry signal to a first output terminal and a scan signal to a second output terminal, in response to a voltage of a first node, a voltage of a second node, and a first clock signal being supplied to a first input terminal, a controller configured to control the voltage of the second node in response to the first clock signal being supplied to the first input terminal, a pull-up part configured to control the voltage of the first node in response to a carry signal of a previous stage being supplied to a second input terminal, and a pull-down part configured to control the voltage of the first node in response to the voltage of the second node and the carry signal of a next stage being supplied to a third input terminal.

Abstract: A method of driving a display panel includes providing a positive polarity data signal to a first data line during an odd-numbered frame, and providing a negative polarity data signal to the first data line during an even-numbered frame. The positive polarity data signal has a first polarity. The negative polarity data signal has a second polarity. Output timing of the positive polarity data signal is different from output timing of the negative polarity data signal.

Abstract: There is provided a display device including a display including a first pixel connected to a first data line and a second pixel connected to a second data line, a data signal generator configured to generate an output signal, and a signal divider configured to divide the output signal, to generate a first data signal and a second data signal, and to apply the first data signal and the second data signal to the first data line and the second data line, respectively, wherein the data signal generator is configured to generate the output signal based on a coupling effect of a first parasitic capacitor formed between the first data line and the second data line and a coupling effect of a parasitic capacitor of a data line formed by the first data line and second data line.

Abstract: A gate driving circuit includes: a pull-up controller applying a carry signal of one of previous stages to a first node in response to the carry signal of the one of the previous stages; a pull-up part outputting a clock signal as an N-th gate output signal; a carry part outputting the clock signal as an N-th carry signal; a first pull-down part pulling down the signal at the first node to a second off voltage; a second pull-down part pulling down the N-th gate output signal to a first off voltage; an inverting part generating an inverting signal based on the clock signal and the second off voltage to output the inverting signal to an inverting node; and a reset part outputting a reset signal to the inverting node.

Abstract: A stage circuit includes a first driver, a second driver, a first output unit, a second output unit and a controller. The first driver controls voltages of first and second nodes, according to a first power source, a third power source, a start signal or a carry signal of a previous stage input to a first input terminal, and a clock signal supplied to a second input terminal. The second driver controls voltages of third and fourth nodes, according to voltages of the first power source, the third power source, the first input terminal and the first and second nodes. The first output unit outputs a carry signal to a first output terminal, according to voltages of the first power source, the second input terminal and the third and fourth nodes. The second output unit outputs a scan signal to a second output terminal, according to voltages of the second power source, the second input terminal and the third and fourth nodes. The controller is electrically coupled to the first output terminal and the second driver.

Abstract: A display device includes a display area including a gate line and a data line and a gate driver connected to an end of the gate line, the gate driver including at least one stages integrated on a substrate configured to output a gate voltage, in which the stage includes an inverter unit and an output unit, in which the output unit includes a first transistor and a first capacitor. The first transistor includes an input terminal applied with a clock signal, a control terminal connected to the node Q, and an output terminal connected to a gate voltage output terminal through which the gate voltage is output. An inverter voltage output from the inverter is lower than the low voltage of the gate voltage output by the output unit.

Abstract: A gate driver, including multiple stages of gate driving circuits, wherein each stage of the gate driving circuits includes an input part configured to generate a Q node signal in response to a carry signal of one of previous stages and a clock signal, the Q node signal being applied to Q node, an output part configured to output a gate output signal to a gate output terminal in response to the Q node signal, and a charge sharing part connected to the gate output terminal of a present stage and a gate output terminal of one of next stages, the charge sharing part configured to operate charge-sharing between the gate output signal of the present stage and a gate output signal of one of the next stages in response to a select signal.

Abstract: A demultiplexer includes: a first transistor connected between a data input terminal and a first output terminal; a second transistor connected between the data input terminal and a second output terminal; and a first pre-charge circuit connected to a gate electrode of the first transistor, the first pre-charge circuit including: a third transistor and a first diode connected between a first clock input terminal and the gate electrode of the first transistor in parallel; and a first capacitor connected between a second clock input terminal and the gate electrode of the first transistor.

Abstract: There is provided a shift register including a plurality of stages sequentially coupled to an input terminal configured to receive a start pulse, wherein each of the plurality of stages includes a first transistor coupled between a first clock input terminal and an output terminal and having a first gate electrode coupled to a first node, a second transistor coupled between the output terminal and a power input terminal and having a second gate electrode coupled to a second clock input terminal, and a third transistor coupled between the first node and a first input terminal configured to receive the start pulse or an output signal of a previous stage of the stages, the third transistor having a third gate electrode coupled to the second clock input terminal.

Abstract: Embodiments relate to a display device including: a first base substrate; gate lines disposed on the first base substrate, the gate lines extending in a first direction; parasitic capacitance electrodes coupled to the gate lines; data lines extending in a second direction crossing the first direction; transistors, each coupled to one of the gate lines and coupled to one of the data lines; and pixels sequentially arranged in the first direction, each of the pixels coupled to a corresponding one of the transistors, respectively. Each of the transistors includes a gate electrode, a source electrode, and a drain electrode, and at least two drain electrodes among the drain electrodes of the transistors each overlap a corresponding one of the parasitic capacitance electrodes in different areas as viewed from a plan view.

Abstract: A gate driver includes a plurality of stage circuits to output a clock signal from the outside as gate signals. A jth stage circuit includes an input unit to charge a first node at an initial voltage when a first input signal is input to a first input terminal, a buffer unit to output the clock signal as a gate signal to an output terminal when the initial voltage is supplied to the first node, a holding unit to maintain the first node at a reset power source level when the clock signal is supplied to the holding unit, and an inverter unit to supply the clock signal or the reset power source to the holding unit. The input unit maintains the first node at a second input signal input voltage to a second input terminal when a third input signal is input to a third input terminal.

Abstract: A display device includes: a first switching element which transmits a first data voltage; a second switching element which transmits a second data voltage; a driving transistor connected to the first switching element and the second switching element, where the driving transistor is driven based on the first data voltage and the second data voltage; and an organic light emitting diode connected to the driving transistor, where the organic light emitting diode emits light based on an output of the driving transistor, and a driving method thereof.

Abstract: A gate circuit according to an exemplary embodiment of the present inventive concept comprises a plurality of stages, each receiving a clock signal and outputting a gate signal and a carry signal. One of the plurality of stages includes a first transistor of which a first terminal and a control terminal are connected to each other and a carry signal of a stage before previous stage is input to the first terminal and the control terminal and a second transistor of which a gate signal of the previous stage is input to a first terminal, a control terminal is connected with a second terminal of the first transistor, and an output terminal is connected to a first node.

Abstract: A coupling compensator for a display panel and a display device including the coupling compensator are disclosed. In one aspect, the coupling compensator includes a memory configured to receive grayscale data and store the grayscale data and a first data converter configured to convert the grayscale data to a plurality of grayscale data voltages including first and second grayscale data voltages. The compensator also includes a coupling voltage calculator configured to calculate a line coupling voltage generated on a data line based on the difference between the first grayscale data voltage corresponding to the grayscale data provided to a first group of the pixels in an (N?1)th row and the second grayscale data voltage corresponding to the grayscale data provided to a first group of the pixels in an Nth row, where the N is an integer equal to or greater than 2.

Abstract: An organic light emitting display device includes a plurality of pixel columns, a first data wiring, a second data wiring, and a power supply wiring. The pixel columns include pixels repeatedly arranged in a first direction, and the pixel columns are repeatedly arranged in a second direction. The first and second directions are substantially perpendicular to each other. The first data wiring extends in the first direction and is connected to the pixels in an even row. The second data wiring extends in the first direction and are connected to the pixels in an odd row. The power supply wiring extends in the first direction between the first and second data wirings.