Abstract: Disclosed herein are a method and apparatus for compressing learning parameters for training of a deep-learning model and transmitting the compressed parameters in a distributed processing environment. Multiple electronic devices in the distributed processing system perform training of a neural network. By performing training, parameters are updated. The electronic device may share the updated parameter thereof with additional electronic devices. In order to efficiently share the parameter, the residual of the parameter is provided to the additional electronic devices. When the residual of the parameter is provided, the additional electronic devices update the parameter using the residual of the parameter.

Abstract: Disclosed herein are a method, apparatus, system, and computer-readable recording medium for image compression. An encoding apparatus performs preprocessing of feature map information, frame packing, frame classification, and encoding. A decoding apparatus performs decoding, frame depacking, and postprocessing in order to reconstruct feature map information. By encoding the feature map information, inter-prediction and intra-block prediction for a frame are performed. The encoding apparatus provides the decoding apparatus with a feature map information bitstream for reconstructing the feature map information along with an image information bitstream.

Abstract: Provided are an image encoding method and device. When carrying out image encoding for a block within a slice, at least one block in a restored block of the slice is set as a reference block. When this is done, the encoding parameters of the reference block are distinguished, and the block to be encoded is encoded adaptively based on the encoding parameters.

Abstract: A capacitor component includes a body having a lamination portion in which first internal electrodes and second internal electrodes are alternately disposed to face each other in a first direction with dielectric layers disposed therebetween, and first and second margin portions disposed on respective opposing sides of the lamination portion in a second direction perpendicular to the first direction. First and second external electrodes are disposed on respective opposing sides of the body in a third direction and are electrically connected to the first and second internal electrodes, respectively. Each of the first and second margin portions includes a reinforcing pattern.

Abstract: A capacitor component includes a body including a dielectric layer, a first electrode and a second internal electrode, laminated in a first direction, opposing each other, and a first cover portion and a second cover portion, disposed on outermost surfaces of the first and second internal electrodes, each having a thickness of 25 ?m or less, a first electrode layer and a second electrode layer, respectively disposed on both external surfaces of the body in a second direction perpendicular to the first direction and respectively, and plating layers, respectively disposed on the first and second electrode layers. A metal oxide is disposed on a boundary between the first electrode layer and the plating layer and a boundary between the second electrode layer and the plating layer.

Abstract: Disclosed are a mutant microorganism for producing succinic acid exhibiting improved activity of conversion of oxaloacetate to malate through the introduction of genes encoding a malate dehydrogenase, wherein an amino acid residue that interacts with a pyrophosphate moiety of NADH through an amide functional group of a main chain of malate dehydrogenase is glutamine (Gln), and a method of producing succinic acid using the same. The mutant microorganism producing succinic acid according to the present invention is capable of producing a high concentration of succinic acid at the highest productivity compared to other mutant microorganisms reported to date when the microorganism is cultured in a limited medium. In addition, the mutant microorganism is capable of producing succinic acid at higher productivity and product concentration through further advanced fermentation technology.

Abstract: A semiconductor package includes a first substrate including a circuit pattern and a dummy pattern on an upper face of the first substrate, a solder ball, a second substrate on the first substrate, and an underfill material layer between the first and second substrates. The underfill material layer wraps around the solder ball. The dummy pattern is not electrically connected to the circuit pattern. The first substrate includes a solder resist layer on the circuit pattern and the dummy pattern. The solder resist layer includes a first opening for exposing at least a part of the circuit pattern. The solder ball is in the first opening and electrically insulated from the dummy pattern by the solder resist layer. The second substrate is electrically connected to the first substrate by the solder ball. The second substrate is electrically insulated from the dummy pattern by the solder resist layer.

Abstract: A film for manufacturing an electronic component includes: a polymer layer; and metal nanowires dispersed in the polymer layer. The polymer layer may include a polyester-based compound such as polyethylene terephthalate. The metal nanowire may include a ferromagnetic metal such as at least one of nickel (Ni), cobalt (Co), and iron (Fe), or alloys thereof.

Abstract: A capacitor component includes a body including dielectric layers, first and second internal electrodes, laminated in a first direction, facing each other, and first and second cover portions, disposed on outermost portions of the first and second internal electrodes, and first and second external electrodes, respectively disposed on both external surfaces of the body in a second direction, perpendicular to the first direction, and respectively connected to the first and second internal electrodes. An indentation including a glass is disposed at at least one of boundaries between the first internal electrodes and the first external electrode or one of boundaries between the second internal electrodes and the second external electrode.

Abstract: A capacitor component includes a body including dielectric layers, first and second internal electrodes, laminated in a first direction, facing each other, and first and second cover portions, disposed on outermost portions of the first and second internal electrodes, and first and second external electrodes, respectively disposed on both external surfaces of the body in a second direction, perpendicular to the first direction, and respectively connected to the first and second internal electrodes. An indentation is disposed at at least one of boundaries between the first internal electrodes and the first external electrode or one of boundaries between the second internal electrodes and the second external electrode.

Abstract: A flash memory device includes a cell array and a control circuit. The cell array includes a first NAND string having first flash memory cells having control gates respectively connected to word lines, and a first bit line selection switch connecting the first flash memory cells to a first bit line according to a control of a first string selection line. The control circuit controls a first erase operation for erasing a selected flash memory cell. The control circuit controls a voltage difference between the first bit line and the first string selection line to have a first value for generating gate induced drain leakage (GIDL) at the first bit line selection switch, and controls a voltage of a control gate of the selected flash memory cell and a voltage of a control gate of an unselected flash memory cell to be different from each other.

Abstract: Provided is a capacitor device, a unit synapse using the capacitor device, a synapse array using the unit synapses. The capacitor device comprises a semiconductor layer which include first and second doping regions formed to be spaced apart from each other and a body region formed between the first and second doping regions; a gate electrode provided above the body region; and a gate insulator stack to have a memory function and disposed between the gate electrode and the semiconductor layer. The capacitance between the gate electrode and the first doping region is determined according to information stored in the gate insulator stack, and the state of the capacitor device is determined according to the capacitance to be one of two preset states. The unit synapse comprises a pair of capacitor devices to perform an XNOR operation.

Abstract: Disclosed is a method of manufacturing a solid oxide fuel cell including a multi-layered electrolyte layer using a calendering process. The method for manufacturing a solid oxide fuel cell is a continuous process, thus providing high productivity and maximizing facility investment and processing costs. In addition, the solid oxide fuel cell manufactured by the method includes an anode that is free of interfacial defects and has a uniform packing structure, thereby advantageously greatly improving the production yield and power density. In addition, the solid oxide fuel cell has excellent interfacial bonding strength between respective layers included therein, and includes a multi-layered electrolyte layer in which the secondary phase at the interface is suppressed and which has increased density, thereby advantageously providing excellent output characteristics and long-term stability even at an intermediate operating temperature.

Abstract: Disclosed herein are relates to a method for compressing a laminate and a method for manufacturing a ceramic electronic component including a laminate. The method for compressing a laminate includes: preparing a laminate; pressurizing the laminate from a first pressure to a second pressure; heating the laminate from a first temperature to a second temperature; maintaining compression of the laminate at the second pressure and the second temperature for a predetermined time; cooling the laminate from the second temperature to a third temperature; and depressurizing the laminate from the second pressure to a third pressure, wherein the second temperature is 70° C. to 150° C.

Abstract: A multilayer capacitor includes a body including a multilayer structure in which a plurality of dielectric layers are provided and a plurality of internal electrodes are stacked with the dielectric layer interposed therebetween and external electrodes disposed outside the body and connected to the plurality of internal electrodes. The body includes a high resistance portion disposed in at least one region between the dielectric layer and the internal electrode and inside the dielectric layer and having electric resistance higher than electric resistance of the internal electrode, and the high resistance portion and the plurality of internal electrodes include the same metal component and the same metal oxide component.

Abstract: A capacitor component includes a body including a layered portion having alternately stacked first and second internal electrodes laminated with dielectric layers interposed therebetween in a first direction, and first and second connecting portions disposed on two opposing surfaces of the layered portion, respectively, in a second direction perpendicular to the first direction and electrically connected to the first and second internal electrodes, respectively. The first and second connecting portions each include a metal layer disposed on the layered portion, a ceramic layer disposed on the metal layer, and an exposed portion penetrating through the ceramic layer to be in contact with the metal layer.

Abstract: A multilayer capacitor includes a body including a dielectric layer and a plurality of internal electrodes stacked on one another with the dielectric layer interposed therebetween, and external electrodes disposed externally on the body, and each connected to the plurality of internal electrodes, wherein at least one of the plurality of internal electrodes includes an alloy region formed in a region in contact with a corresponding external electrode of the external electrodes, and the alloy region includes a nickel (Ni)-chromium (Cr) alloy.

Abstract: Provided is a complementary sensors-integrated interface circuit and a differential circuit using the same. The complementary sensors-integrated interface circuit includes: a first sensor having a sensing characteristic for a detection target material; and a second sensor having a sensing characteristic complementary to that of the first sensor for the detection target material, wherein the first sensor is composed of an FET-type sensor, the second sensor is composed of an FET-type sensor or a resistor-type sensor, and the first sensor and the second sensor are connected in series. The interface circuit having the above-described configuration increases the change in output voltage, thereby improving the sensing sensitivity. The complementary sensors-integrated interface circuit is characterized in that it serves as an amplification circuit.

Abstract: A ceramic electronic component includes a body including a dielectric layer and an internal electrode; and an external electrode disposed on the body and connected to the internal electrode. The dielectric layer has a perovskite structure represented by a general formula ABO3 as a main phase, and includes a region in which Dy is solid solubilized. In the region in which the Dy is solid solubilized, an X-ray count of Dy solid-solubilized in an A-site of the perovskite structure measured by using Scanning Transmission Electron Microscopy-Energy Dispersive X-ray Spectroscopy (STEM-EDS) is AD, an X-ray count of Dy solid-solubilized in a B-site of the perovskite structure is BD, and an average value of AD/BD is 1.6 or more and 2.0 or less.

Abstract: A ceramic electronic component includes a body including a dielectric layer and an internal electrode; and an external electrode disposed on the body and connected to the internal electrode. The dielectric layer has a perovskite structure represented by a general formula ABO3 as a main phase, and includes a region in which Dy is dissolved. In the region in which Dy is dissolved, an atomic ratio of a content of Dy dissolved in an A-site of the perovskite structure to a content of Dy dissolved in a B-site is 1.6 or more and 2.0 or less.