Abstract: A memory device includes a memory cell array comprising a weight cell array including a plurality of first weight cell pairs and a reference cell array including a plurality of reference cell pairs, and an analog-to-digital converter (ADC) connected to the plurality of first weight cell pairs and the plurality of reference cell pairs, and configured to output a signal representing a weighted sum of at least one weight value among a plurality of weight values stored in the plurality of first weight cell pairs and at least one reference value among a plurality of reference values stored in the plurality of reference cell pairs in response to activation of at least one corresponding first weight cell word line among a plurality of first weight cell word lines and at least one corresponding reference cell word line among a plurality of reference cell word lines during a read operation.

Abstract: Provided is a 3D stackable synapse string. The 3D stackable synapse string includes: a channel hole having a pillar shape extending in a vertical direction and filled with an insulating material; a first synapse string provided on a first surface of an outer peripheral surface of the channel hole, the first synapse string including a plurality of first synapse devices stacked along a vertical direction of the channel hole; a second synapse string provided on a second surface of the outer peripheral surface of the channel hole, the second synapse string including a plurality of second synapse devices stacked along the vertical direction of the channel hole; and a device isolation portion provided on the outer peripheral surface of the channel hole between the first and second synapse strings. The two synapse strings are electrically separated from each other by the device isolation portion.

Abstract: Provided is a capacitor device, a unit synapse using the capacitor device, a synapse array using the unit synapses. The capacitor device comprises a semiconductor layer which include first and second doping regions formed to be spaced apart from each other and a body region formed between the first and second doping regions; a gate electrode provided above the body region; and a gate insulator stack to have a memory function and disposed between the gate electrode and the semiconductor layer. The capacitance between the gate electrode and the first doping region is determined according to information stored in the gate insulator stack, and the state of the capacitor device is determined according to the capacitance to be one of two preset states. The unit synapse comprises a pair of capacitor devices to perform an XNOR operation.

Abstract: Provided is a 3D synapse device stack, a 3D stackable synapse array using the same, and a method for manufacturing the 3D synapse device stack.

Abstract: The present specification relates to a connecting pipe connected to pipes. In one embodiment, the connecting pipe may comprise: a first opening; a second opening; and a support groove which is vertical to the transverse cross section of the first opening, and which is disposed on a first center line passing through the center of the transverse cross section of the first opening. When the connecting pipe according to embodiments is connected to the pipes, the possibility of breakage or deformation, which can occur at a connecting portion of the connecting pipe and the pipe, can be minimized.

Abstract: A flash memory device includes a cell array and a control circuit. The cell array includes a first NAND string having first flash memory cells having control gates respectively connected to word lines, and a first bit line selection switch connecting the first flash memory cells to a first bit line according to a control of a first string selection line. The control circuit controls a first erase operation for erasing a selected flash memory cell. The control circuit controls a voltage difference between the first bit line and the first string selection line to have a first value for generating gate induced drain leakage (GIDL) at the first bit line selection switch, and controls a voltage of a control gate of the selected flash memory cell and a voltage of a control gate of an unselected flash memory cell to be different from each other.

Abstract: Provided is a complementary sensors-integrated interface circuit and a differential circuit using the same. The complementary sensors-integrated interface circuit includes: a first sensor having a sensing characteristic for a detection target material; and a second sensor having a sensing characteristic complementary to that of the first sensor for the detection target material, wherein the first sensor is composed of an FET-type sensor, the second sensor is composed of an FET-type sensor or a resistor-type sensor, and the first sensor and the second sensor are connected in series. The interface circuit having the above-described configuration increases the change in output voltage, thereby improving the sensing sensitivity. The complementary sensors-integrated interface circuit is characterized in that it serves as an amplification circuit.

Abstract: Provided is an analog-to-digital converter. The ADC includes a plurality of bit detection units. Each of the bit detection unit comprises: a state level determination module including a semiconductor device with a preset threshold voltage to receive an input signal; and an output module connected to the state level determination module and configured to detect and output a binary value corresponding to the input voltage. The bit detection units are configured to match one-to-one with the bits constituting a digital code, respectively. The state level determination module is configured to have a threshold voltage or conductance determined according to the bit of the digital code matched to the bit detection unit. Each of the bit detection units detects and outputs a binary value corresponding to the matched bit of the digital code from the input signal.

Abstract: The present invention relates to an antibody or antigen-binding fragment thereof that targets cotinine, a chimeric antigen receptor comprising same, and uses thereof. The antibody of the present invention is an antibody that specifically binds to cotinine, and in particular, an antibody that binds more specifically to the S-isomer of cotinine than to the R-isomer thereof. In addition, the antibody has very low homology and a unique sequence, compared to the CDR sequences of conventional cotinine target antibodies. Cells expressing a chimeric antigen receptor comprising the anti-cotinine antibody or antigen-binding fragment of the present invention bind to a cotinine-conjugated switch and respond to a target cell line, thereby inducing immune cell activity. Therefore, the antibody or antigen-binding fragment thereof of the present invention can be used to suppress immune side effects due to overactivation of T cells through cotinine-mediated activation regulation of chimeric antigen receptor effector cells.

Abstract: Provided is a method for reconfiguring the oxygen concentration of a metal oxide. The method includes the steps of: (a) predetermining the oxygen reconfiguration voltage to ensure that the metal oxide has the required electron concentration or oxygen adsorption or desorption energy for a chemical reaction; (b) applying voltages to the contact and separation electrodes according to the oxygen reconfiguration voltage; (c) predetermining the oxygen concentration recovery voltage based on the chemical reaction; and (d) after the chemical reaction, applying voltages to the contact and separation electrodes according to the oxygen concentration recovery voltage. This method allows for the reconfiguration of the oxygen concentration in the metal oxide by adjusting the electron concentration and controlling the oxygen adsorption or desorption energy of the metal oxide.

Abstract: Provided is a sensing method of a FET-type sensor using electric charge storage engineering. The sensing method comprises the following steps to improve reactivity and selectivity to a gas to be sensed: (a) applying a preset erase voltage (Erase bias) or program voltage (Program bias) to the control gate according to the type of gas to be sensed to change a threshold voltage of the FET transducer and control the charge at an interface between the passivation layer and the sensing material layer; and (b) in the recovery phase where the gas detection reaction is terminated and the original state is returned, applying a pre-bias greater or less than a read voltage to the control gate according to the type of gas detected, and then applying the read voltage to the drain and the source of the FET transducer to increase the desorption rate of the detected gas.

Abstract: Provided is a ferroelectric-based synaptic device and a three-dimensional synaptic device stack using the same. The synaptic device includes a source, a drain, a semiconductor body in which a channel region are formed, a gate electrode, and an insulating layer stack disposed between the semiconductor body and the gate electrode. The insulating layer stack includes: a charge trap layer disposed on the channel region of the semiconductor body and is made of a material capable of storing or trapping electric charges; a ferroelectric layer made of a ferroelectric material; and an insulating layer disposed between the charge trap layer and the ferroelectric layer. The synaptic device is characterized in that weight information is volatilely stored in the charge trap layer and non-volatilely stored in the ferroelectric layer.

Abstract: A neuromorphic system enabling on-chip training includes: synapse arrays where synapse devices are arranged in a cross-bar shape; a final neuron layer including a forward neuron and a backward neuron and connected to an output terminal of a last synapse array; neuron layers including a forward neuron, a backward neuron, and a memory storing signals used during a weighted value update operation of a neural network and arranged between the remaining synapse arrays except for a first and last synapse arrays; and an error calculation circuit detecting and outputting an error value of a target signal and an output signal of the forward neuron of the final neuron layer. Conductances of the synapse devices represent weighted values of the neural network and are changed by the weighted value update operation. Each synapse device is configured with a flash device, and the neuron layers are implemented with ultra-miniature devices.

Abstract: Provided is a synaptic array structure. The synaptic array structure includes: an isolation insulating layer positioned in a predetermined area on a semiconductor substrate to isolate devices; TFT-type synaptic devices arranged in an array on an isolation insulating layer; and CMOS peripheral circuits provided on the semiconductor substrate. The TFT-type synaptic device includes: a source and a drain positioned on the isolation insulating layer; a semiconductor body positioned between the source and the drain; oxide layers positioned between the semiconductor body and the source/drain; a semiconductor layer for channel; a TFT gate insulating layer; and a TFT gate electrode. The present invention, based on CMOS integration technology, processes TFT-type synaptic devices and CMOS peripheral circuits together, thereby reducing the number of masks and fabrication steps used during the fabricating process.

Abstract: Provided is a synaptic array structure. The synaptic array structure includes: an isolation insulating layer positioned in a predetermined area on a semiconductor substrate to isolate devices; TFT-type synaptic devices arranged in an array on an isolation insulating layer; and CMOS peripheral circuits provided on the semiconductor substrate. The TFT-type synaptic device includes: a source and a drain positioned on the isolation insulating layer; a semiconductor body positioned between the source and the drain; oxide layers positioned between the semiconductor body and the source/drain; a semiconductor layer for channel; a TFT gate insulating layer; and a TFT gate electrode. The present invention, based on CMOS integration technology, processes TFT-type synaptic devices and CMOS peripheral circuits together, thereby reducing the number of masks and fabrication steps used during the fabricating process.

Abstract: A synapse string includes first and second cell strings each having a plurality of memory cell elements connected in series and first switch elements connected to first or second ends of the first and second cell strings, respectively. The memory cell elements of the first cell string and the memory cell elements of the second cell string are in a one-to-one correspondence, and a pair of the memory cell elements being in a one-to-one correspondence has terminals to which a read voltage is applied connected to each other to constitute one synapse morphic element, so that the synapse string includes a plurality of synapse morphic elements connected in series. A synapse string array architecture enables forward propagation and backward propagation by implementing high-density synapse strings, so that the synapse string array architecture can be applied to a neural network capable of inferencing and on-chip learning, along with inference and recognition.

Abstract: Provided is a ferroelectric-based synaptic device and a three-dimensional synaptic device stack using the same. The synaptic device includes a source, a drain, a semiconductor body in which a channel region are formed, a gate electrode, and an insulating layer stack disposed between the semiconductor body and the gate electrode. The insulating layer stack includes: a charge trap layer disposed on the channel region of the semiconductor body and is made of a material capable of storing or trapping electric charges; a ferroelectric layer made of a ferroelectric material; and an insulating layer disposed between the charge trap layer and the ferroelectric layer. The synaptic device is characterized in that weight information is volatilely stored in the charge trap layer and non-volatilely stored in the ferroelectric layer.

Abstract: A flash memory device includes a cell array and a control circuit. The cell array includes a first NAND string having first flash memory cells having control gates respectively connected to word lines, and a first bit line selection switch connecting the first flash memory cells to a first bit line according to a control of a first string selection line. The control circuit controls a first erase operation for erasing a selected flash memory cell. The control circuit controls a voltage difference between the first bit line and the first string selection line to have a first value for generating gate induced drain leakage (GIDL) at the first bit line selection switch, and controls a voltage of a control gate of the selected flash memory cell and a voltage of a control gate of an unselected flash memory cell to be different from each other.

Abstract: Provided is a capacitor device, a unit synapse using the capacitor device, a synapse array using the unit synapses. The capacitor device comprises a semiconductor layer which include first and second doping regions formed to be spaced apart from each other and a body region formed between the first and second doping regions; a gate electrode provided above the body region; and a gate insulator stack to have a memory function and disposed between the gate electrode and the semiconductor layer. The capacitance between the gate electrode and the first doping region is determined according to information stored in the gate insulator stack, and the state of the capacitor device is determined according to the capacitance to be one of two preset states. The unit synapse comprises a pair of capacitor devices to perform an XNOR operation.

Abstract: Provided is a complementary sensors-integrated interface circuit and a differential circuit using the same. The complementary sensors-integrated interface circuit includes: a first sensor having a sensing characteristic for a detection target material; and a second sensor having a sensing characteristic complementary to that of the first sensor for the detection target material, wherein the first sensor is composed of an FET-type sensor, the second sensor is composed of an FET-type sensor or a resistor-type sensor, and the first sensor and the second sensor are connected in series. The interface circuit having the above-described configuration increases the change in output voltage, thereby improving the sensing sensitivity. The complementary sensors-integrated interface circuit is characterized in that it serves as an amplification circuit.