Abstract: Disclosed is a method of manufacturing a solid oxide fuel cell including a multi-layered electrolyte layer using a calendering process. The method for manufacturing a solid oxide fuel cell is a continuous process, thus providing high productivity and maximizing facility investment and processing costs. In addition, the solid oxide fuel cell manufactured by the method includes an anode that is free of interfacial defects and has a uniform packing structure, thereby advantageously greatly improving the production yield and power density. In addition, the solid oxide fuel cell has excellent interfacial bonding strength between respective layers included therein, and includes a multi-layered electrolyte layer in which the secondary phase at the interface is suppressed and which has increased density, thereby advantageously providing excellent output characteristics and long-term stability even at an intermediate operating temperature.

Abstract: Disclosed herein are relates to a method for compressing a laminate and a method for manufacturing a ceramic electronic component including a laminate. The method for compressing a laminate includes: preparing a laminate; pressurizing the laminate from a first pressure to a second pressure; heating the laminate from a first temperature to a second temperature; maintaining compression of the laminate at the second pressure and the second temperature for a predetermined time; cooling the laminate from the second temperature to a third temperature; and depressurizing the laminate from the second pressure to a third pressure, wherein the second temperature is 70° C. to 150° C.

Abstract: A capacitor component includes a body including a layered portion having alternately stacked first and second internal electrodes laminated with dielectric layers interposed therebetween in a first direction, and first and second connecting portions disposed on two opposing surfaces of the layered portion, respectively, in a second direction perpendicular to the first direction and electrically connected to the first and second internal electrodes, respectively. The first and second connecting portions each include a metal layer disposed on the layered portion, a ceramic layer disposed on the metal layer, and an exposed portion penetrating through the ceramic layer to be in contact with the metal layer.

Abstract: A multilayer capacitor includes a body including a multilayer structure in which a plurality of dielectric layers are provided and a plurality of internal electrodes are stacked with the dielectric layer interposed therebetween and external electrodes disposed outside the body and connected to the plurality of internal electrodes. The body includes a high resistance portion disposed in at least one region between the dielectric layer and the internal electrode and inside the dielectric layer and having electric resistance higher than electric resistance of the internal electrode, and the high resistance portion and the plurality of internal electrodes include the same metal component and the same metal oxide component.

Abstract: A multilayer capacitor includes a body including a dielectric layer and a plurality of internal electrodes stacked on one another with the dielectric layer interposed therebetween, and external electrodes disposed externally on the body, and each connected to the plurality of internal electrodes, wherein at least one of the plurality of internal electrodes includes an alloy region formed in a region in contact with a corresponding external electrode of the external electrodes, and the alloy region includes a nickel (Ni)-chromium (Cr) alloy.

Abstract: Provided is a complementary sensors-integrated interface circuit and a differential circuit using the same. The complementary sensors-integrated interface circuit includes: a first sensor having a sensing characteristic for a detection target material; and a second sensor having a sensing characteristic complementary to that of the first sensor for the detection target material, wherein the first sensor is composed of an FET-type sensor, the second sensor is composed of an FET-type sensor or a resistor-type sensor, and the first sensor and the second sensor are connected in series. The interface circuit having the above-described configuration increases the change in output voltage, thereby improving the sensing sensitivity. The complementary sensors-integrated interface circuit is characterized in that it serves as an amplification circuit.

Abstract: A ceramic electronic component includes a body including a dielectric layer and an internal electrode; and an external electrode disposed on the body and connected to the internal electrode. The dielectric layer has a perovskite structure represented by a general formula ABO3 as a main phase, and includes a region in which Dy is dissolved. In the region in which Dy is dissolved, an atomic ratio of a content of Dy dissolved in an A-site of the perovskite structure to a content of Dy dissolved in a B-site is 1.6 or more and 2.0 or less.

Abstract: A ceramic electronic component includes a body including a dielectric layer and an internal electrode; and an external electrode disposed on the body and connected to the internal electrode. The dielectric layer has a perovskite structure represented by a general formula ABO3 as a main phase, and includes a region in which Dy is solid solubilized. In the region in which the Dy is solid solubilized, an X-ray count of Dy solid-solubilized in an A-site of the perovskite structure measured by using Scanning Transmission Electron Microscopy-Energy Dispersive X-ray Spectroscopy (STEM-EDS) is AD, an X-ray count of Dy solid-solubilized in a B-site of the perovskite structure is BD, and an average value of AD/BD is 1.6 or more and 2.0 or less.

Abstract: A multilayer ceramic capacitor includes a ceramic body including dielectric layers, a plurality of internal electrodes disposed in the ceramic body, and a first side margin portion and a second side margin portion respectively arranged on end portions of the internal electrodes exposed to first and second surfaces. The first and second side margin portions each include a first region adjacent to an outward facing side surface of the respective side margin portion, and a second region adjacent to the internal electrodes exposed to the first and second surfaces of the ceramic body, and an average size of dielectric grains included in the second region is larger than an average size of dielectric grains included in the first region.

Abstract: A multilayer electronic component includes a body including dielectric layers and internal electrodes. The internal electrodes are exposed to fifth and sixth surfaces of the body, and first ends thereof are respectively exposed to third or fourth surfaces of the body. First and second side margin portions are respectively disposed on the fifth and sixth surfaces. The body includes an active portion, and upper and lower cover portions disposed respectively on a first surface and a second surface of the active portion in a first direction. The ratio of a dimension of the lower cover portion in the first direction C to a dimension of the first side margin portion in the third direction A, C/A?2.6, C/T is 0.080, where T is a dimension of the body in the first direction, and D<C where D is the dimension of the body in the first direction.

Abstract: Provided is a 3D stackable synapse string, a 3D stackable synapse array using the same, and a method for manufacturing the 3D stackable synapse string.

Abstract: Provided is a 3D synapse device stack, a 3D stackable synapse array using the same, and a method for manufacturing the 3D synapse device stack.

Abstract: Provided is a 3D synapse device stack, a 3D stackable synapse array using the same, and a method for manufacturing the 3D synapse device stack.

Abstract: Provided is a 3D capacitor stack and a method for manufacturing the same. The 3D capacitor stack comprises: a drain line electrode having a pillar shape provided in a vertical direction on a substrate surface; a plurality of first insulating layers positioned in first region of an outer circumferential surface of the drain line electrode; a plurality of drains positioned in second regions of an outer circumferential surface of the drain line electrode; a plurality of insulator stacks positioned on side surfaces of the drains; and a plurality of word lines positioned on side surfaces of the insulator stacks.

Abstract: A capacitor component includes a body including a dielectric layer, a layering portion in which first and second internal electrodes opposing each other are layered in a first direction, and first and second connecting portions disposed on both surfaces of the layering portion taken in a second direction perpendicular to the first direction and connected to the first and second internal electrodes, respectively; and first and second external electrodes disposed on the first and second connecting portions, respectively, and the first and second external electrodes include metal powder particles, a surface of each of which is coated with at least one of graphene and carbon nanotubes.

Abstract: A multilayer ceramic capacitor includes a ceramic body including a dielectric layer, a plurality of internal electrodes disposed in the ceramic body, and a first side margin portion and a second side margin portion respectively arranged on end portions of the internal electrodes exposed from first and second surfaces. The first and second side margin portions respectively include a first region adjacent to an outer side surface of each of the side margin portions, and a second region adjacent to the internal electrodes exposed from the first and second surfaces. The number of pores per unit area in the second region is less than the number of pores per unit area in the first region.

Abstract: A multilayer capacitor includes a ceramic body including a dielectric layer, and having first to sixth surfaces, connected to the first surface to the fourth surface and opposing each other, a plurality of internal electrodes disposed inside the ceramic body, exposed to the fifth surface and the sixth surface, and having one ends exposed to the third surface or the fourth surface, and a first side margin portion and a second side margin portion disposed on end portions of the internal electrode, exposed to the fifth surface and the sixth surface, the first and second side margin portions are divided into an inner layer formed to be adjacent to the ceramic body, and an outer layer formed on the inner layer, and a dielectric constant of the inner layer is lower than a dielectric constant of the outer layer.

Abstract: A capacitor component includes a body having a lamination portion in which first internal electrodes and second internal electrodes are alternately disposed to face each other in a first direction with dielectric layers disposed therebetween, and first and second margin portions disposed on respective opposing sides of the lamination portion in a second direction perpendicular to the first direction. First and second external electrodes are disposed on respective opposing sides of the body in a third direction and are electrically connected to the first and second internal electrodes, respectively. Each of the first and second margin portions includes a reinforcing pattern.

Abstract: Disclosed is a method for analyzing a sulfide-based solid electrolyte using computer simulation including connecting, by a user, to a client accessible to a server, inputting information of a sulfide-based solid electrolyte to be analyzed to the client, transmitting, by the client, the information to the server, implementing, by the server, generation of a three-dimensional structure in which anion clusters and lithium ions are disposed, based on the transmitted information, feeding back, by the server, an implementation result to the client, and displaying, by the client, the feedback result. In addition, properties of sulfide-based solid electrolytes, which cannot be observed by experimentation, can be analyzed based on lithium, ion conductivity.

Abstract: A multilayer capacitor includes a body including a multilayer structure in which a plurality of dielectric layers are stacked, and further including a plurality of internal electrodes having a dielectric layer interposed therebetween and external electrodes disposed on external surfaces of the body and connected to the internal electrodes. The body further includes an active portion in which the plurality of internal electrodes are located to form capacitance and a side margin portion covering a first surface and a second surface of the active portion opposing each other. An average grain size of a dielectric layer included in the active portion is different from an average grain size of a dielectric layer included in the margin portion. The side margin portion includes an extending portion extending between the external electrodes and the internal electrodes to cover a portion of the internal electrodes.