Abstract: In one embodiment, the converter is configured to receive a first sync signal from a display driver and to convert the first sync signal into a second sync signal. The second sync signal is for controlling image sensing.

Abstract: A portable electronic device comprises a double-sided display including a first display side and a second display side formed on a side opposite the first display side; a direct memory access (DMA) controller configured to read first image data from a memory; at least one sensor configured to detect at least one of a position change of the double-sided display and a movement of a user's pupil and to output a detection signal; a status signal generator configured to interpret the detection signal output and to output a status signal; a transmission order determiner configured to receive the first image data from the DMA controller, to determine a transmission order of the first image data based on the status signal, and to output second image data corresponding to the determined transmission order; and a display driver integrated circuit (IC) configured to transmit the second image data to the display.

Abstract: A system on chip (SoC) includes a first display subsystem configured to perform first and second imaging functions and a second display subsystem configured to only perform the first imaging function. The SoC is configured to activate one of the display subsystems and deactivate the other display subsystem based on a comparison of a current frame of image data and a previous frame of image data.

Abstract: A display panel controller includes a display driver integrated circuit that drives a display panel to display a still image at a predetermined frame rate, an application processor that provides the display driver integrated circuit with still image data for implementing the still image and a plurality of control signals generated by a timing controller, and a synchronization controller that controls a frame synchronization of the display panel based on a minimum refresh rate of the display panel.

Abstract: A system on chip (SoC) for transmitting data packets to a display driver integrated circuit (IC) controlling a plurality of displays is provided. The SoC includes a first register, and a central processing unit (CPU) configured to set first values in the first register to adjust a frame rate of each of the displays. A tearing effect (TE) signal detection circuit is configured to detect a TE signal output from the display driver IC. A data transmission circuit is configured to generate a plurality of frame rate adjustment signals using the detected TE signal and the first values and to control transmission timings of the data packets transmitted to the displays using the frame rate adjustment signals.

Abstract: In one example embodiment, a method of operating an image data processing circuit which controls an operation of an organic light-emitting diode (OLED) display includes transforming at least one first RGB value into at least one luminance value and at least one chroma value. The method further includes adjusting the at least one luminance value and the at least one chroma value based on at least one first control value. The method further includes generating at least one second RGB value based on the at least one adjusted luminance value and the at least one adjusted chroma value. The method further includes outputting the second RGB values to the OLED display.

Abstract: A display system is provided. The display system includes a perframe controller configured to receive a frame synchronization signal and to change values of M and N in synchronization with at least one pulse of the frame synchronization signal, where M and N are natural numbers; and a fractional divider configured to generate and output a pixel clock signal by dividing an input clock signal by a division ratio of N/M.

Abstract: Provided are an interconnect, a bus system with interconnect, and bus system operating method. The bus system includes a master, slaves access by the master, and an interconnect. The interconnect connects the master with the slaves in response to selection bits identified in a master address provided by the master.

Abstract: Provided are a display device and a method for updating an image of the same. The display device includes a display unit, a processing unit for compressing both image data corresponding to an updated region of the display unit and image data corresponding to a peripheral region adjacent to the updated region together and generating compressed image data, and a display driving unit for receiving the compressed image data and decompressing the image data, wherein the display unit displays an image corresponding to the updated region by the decompressed image data.

Abstract: A display controller includes a scaler which is configured to receive a frame image, scale up the frame image to generate a high resolution frame image based on a quality of the frame image and information about a display device, and output the frame image or the high resolution frame image to the display device for display. A method of controlling image display includes: receiving a frame image; determining whether to scale up the frame image to generate a high resolution frame image based on a quality of the frame image and information about a display device; scaling up the frame image according to a result of the determining; and outputting the frame image or the high resolution frame image for display at the display device.

Abstract: A display controller includes a merger and an alpha blender. The merger is configured to mix a first left frame including first left pixel data and a first right frame including first right pixel data based on a three-dimensional (3D) display format, and further configured and to output a first mixed frame and a second mixed frame. The alpha blender is configured to blend the first mixed frame and the second mixed frame to produce a first blended frame.

Abstract: In one embodiment, the converter is configured to receive a first sync signal from a display driver and to convert the first sync signal into a second sync signal. The second sync signal is for controlling image sensing.

Abstract: The display controller includes a decoder, a control circuit, and a video output logic circuit. The decoder is configured to decode a first display command and output a decoding signal and first synchronizing information indicating the first display command is received. The control circuit is configured to generate a first control signal based on second synchronizing information and the decoding signal. The second synchronizing information is output from a second display controller and indicates a second display command is received. The video output logic circuit is configured to send a part of video data stored in a video source and a plurality of first timing control signals for displaying the part of the video data on a display to the display based on the first control signal.

Abstract: A camera module includes an image sensor configured to convert an optical signal received through a lens into an electrical signal and generate full-size image data, an image signal processing unit configured to calibrate and output the full-size image data, a first memory unit configured to periodically receive and store the full-size image data from the image signal processing unit, a scaling unit configured to scale down the full-size image data received from the first memory unit and periodically output scaled-down image data to a display device, and an encoder configured to receive the full-size image data stored in the first memory unit, convert it into a compressed file in a predetermined format, and output the compressed file upon opening of a shutter.

Abstract: A device includes a plurality of display modules configured to commonly receive a stream of video data from a controller and a video control masking unit. Each display module includes a display device. The video control masking unit receives one or more control signals that indicate how the video data is to be displayed by the display modules, and further receives at least one of: a clock signal for clocking the stream of video data that is provided in common to the plurality of display modules, and a data enable signal for enabling the display modules to process the video data; and in response thereto the video control masking unit masks at least one of the clock signal and the data enable signal to generate a plurality of masked signals each corresponding to one of the display modules, and provides each of the masked signals to the corresponding display module.

Abstract: A system on chip (SoC) and a method of operating the same are provided. The SoC includes a central processing unit (CPU) controlling a memory operation and a display operation on a current frame of an image based on generation of the image and an interrupt signal; an image generator requesting data of the current frame from a memory according to control of the CPU; a UD unit determining whether the current frame is updated, detecting whether an update region is a partial frame based on virtual addresses included in a request of the image generator, and outputting the interrupt signal corresponding to the update region to the CPU; a memory controller storing the update region in the memory according to the control of the CPU; and a display controller accessing the memory and outputting the update region to a display device according to the control of the CPU.

Abstract: A scaler is provided and includes filters each receiving input pixel data and scaling the input pixel data using a scaling factor to generate a scaled pixel value, and a plurality of mixers, less than the plurality of filters. A first mixer performs a first blending operation on a first scaled pixel value and a second scaled pixel value provided by different filters. A second mixer performs a second blending operation on the blended result of the first mixer and a third scaled pixel value provided by anther filter.

Abstract: Provided are an interconnect, a bus system with interconnect, and bus system operating method. The bus system includes a master, slaves access by the master, and an interconnect. The interconnect connects the master with the slaves in response to selection bits identified in a master address provided by the master.

Abstract: Multi-processor systems and methods thereof are provided. In an example, the multi-processor system may include a boot memory including a plurality of boot codes, each of the plurality of boot codes configured to facilitate an initialization process at one of a plurality of intellectual property (IP) blocks, each of the plurality of IP blocks having shared access to the boot memory. In another example, the multi-processor system may receive, from a first processor, a request to provide one of a plurality of boot codes from a boot memory, the received request sent in response to a system initializing signal, may read the requested boot code from the boot memory and may transfer, from a second processor, the read boot code to the first processor.

Abstract: An image processing device includes a first image enhancer and a second image enhancer. The first image enhancer receives first image data and generates first image enhancement information by analyzing the first image data. The second image enhancer receives second image data and generates second image enhancement information by analyzing the second image data. The first image enhancer converts the first image data into first enhanced image data based on the first image enhancement information and the second image enhancement information. The second image enhancer converts the second image data into second enhanced image data based on the first image enhancement information and the second image enhancement information.