Abstract: A device includes a plurality of display modules configured to commonly receive a stream of video data from a controller and a video control masking unit. Each display module includes a display device. The video control masking unit receives one or more control signals that indicate how the video data is to be displayed by the display modules, and further receives at least one of: a clock signal for clocking the stream of video data that is provided in common to the plurality of display modules, and a data enable signal for enabling the display modules to process the video data; and in response thereto the video control masking unit masks at least one of the clock signal and the data enable signal to generate a plurality of masked signals each corresponding to one of the display modules, and provides each of the masked signals to the corresponding display module.

Abstract: An image processor for combining video data and graphic data is provided. The image processor includes a scaler that is configured to scale compressed graphic data in a horizontal direction using bilinear scaling, to scale a horizontally scaled graphic data in a vertical direction using line copy, and to process a data value of a pixel at a border of a vertically scaled graphic data based on a data value of the compressed graphic data and a data combiner that is configured to combine video data with processed graphic data output from the scaler.

Abstract: A system including an operating speed detection apparatus, an operating speed detection apparatus and method thereof. In the example method, a received clock signal may be delayed to generate a plurality of delayed clock signals. A plurality of detection signals may be generated based on the plurality of delayed clock signals and the received clock signal. An operating speed (e.g., of a system) may be determined based at least in part on the plurality of detection signals. In an example, the example method may be performed by an operating speed detection apparatus. In another example, the example method may be performed by a system including the operating speed detection apparatus.

Abstract: An image display system includes: a frame buffer having a plurality of lines, each of which stores image data and repetition information of the image data; a memory controller in signal communication with the frame buffer for reading the image data and the repetition information from the frame buffer; a display controller in signal communication with the memory controller for regenerating the image data, which is provided from the memory controller, in accordance with the repetition information provided from the memory controller; and a display device in signal communication with the display controller for displaying the regenerated image data, which is provided from the display controller, under regulation by the display controller.

Abstract: An image display system includes: a frame buffer including plurality of lines; a memory controller conducting writing and reading operations with the frame buffer; an image data provider supplying image data to the memory controller and generating a writing address; a display controller generating a reading address and receiving image data that is read from the frame buffer by the memory controller; a tearing-protection bus arbiter storing a burst length, receiving the writing and reading addresses, and selectively outputting the writing and reading addresses; and a display device displaying the image data by the display controller. The reading address contains a start address for the reading operation and the writing address contains a start address for the writing operation.

Abstract: Multi-processor systems and methods thereof are provided. In an example, the multi-processor system may include a boot memory including a plurality of boot codes, each of the plurality of boot codes configured to facilitate an initialization process at one of a plurality of intellectual property (IP) blocks, each of the plurality of IP blocks having shared access to the boot memory. In another example, the multi-processor system may receive, from a first processor, a request to provide one of a plurality of boot codes from a boot memory, the received request sent in response to a system initializing signal, may read the requested boot code from the boot memory and may transfer, from a second processor, the read boot code to the first processor.

Abstract: A system including an operating speed detection apparatus, an operating speed detection apparatus and method thereof. In the example method, a received clock signal may be delayed to generate a plurality of delayed clock signals. A plurality of detection signals may be generated based on the plurality of delayed clock signals and the received clock signal. An operating speed (e.g., of a system) may be determined based at least in part on the plurality of detection signals. In an example, the example method may be performed by an operating speed detection apparatus. In another example, the example method may be performed by a system including the operating speed detection apparatus.