Abstract: Provided are an interconnect, a bus system with interconnect, and bus system operating method. The bus system includes a master, slaves access by the master, and an interconnect. The interconnect connects the master with the slaves in response to selection bits identified in a master address provided by the master.

Abstract: In one example embodiment, a method of operating an image data processing circuit which controls an operation of an organic light-emitting diode (OLED) display includes transforming at least one first RGB value into at least one luminance value and at least one chroma value. The method further includes adjusting the at least one luminance value and the at least one chroma value based on at least one first control value. The method further includes generating at least one second RGB value based on the at least one adjusted luminance value and the at least one adjusted chroma value. The method further includes outputting the second RGB values to the OLED display.

Abstract: Multi-processor systems and methods thereof are provided. In an example, the multi-processor system may include a boot memory including a plurality of boot codes, each of the plurality of boot codes configured to facilitate an initialization process at one of a plurality of intellectual property (IP) blocks, each of the plurality of IP blocks having shared access to the boot memory. In another example, the multi-processor system may receive, from a first processor, a request to provide one of a plurality of boot codes from a boot memory, the received request sent in response to a system initializing signal, may read the requested boot code from the boot memory and may transfer, from a second processor, the read boot code to the first processor.

Abstract: A system on chip (SoC) includes a first display subsystem configured to perform first and second imaging functions and a second display subsystem configured to only perform the first imaging function. The SoC is configured to activate one of the display subsystems and deactivate the other display subsystem based on a comparison of a current frame of image data and a previous frame of image data.

Abstract: An image processor for combining video data and graphic data is provided. The image processor includes a scaler that is configured to scale compressed graphic data in a horizontal direction using bilinear scaling, to scale a horizontally scaled graphic data in a vertical direction using line copy, and to process a data value of a pixel at a border of a vertically scaled graphic data based on a data value of the compressed graphic data and a data combiner that is configured to combine video data with processed graphic data output from the scaler.

Abstract: An image display system includes: a frame buffer having a plurality of lines, each of which stores image data and repetition information of the image data; a memory controller in signal communication with the frame buffer for reading the image data and the repetition information from the frame buffer; a display controller in signal communication with the memory controller for regenerating the image data, which is provided from the memory controller, in accordance with the repetition information provided from the memory controller; and a display device in signal communication with the display controller for displaying the regenerated image data, which is provided from the display controller, under regulation by the display controller.

Abstract: A display controller includes a synchronization signal adjusting circuit, which adjusts at least one of the delay and the pulse width of a synchronization signal generated in a display driver and outputs an adjusted synchronization signal, and a transmission timing control circuit configured to control the transmission timing of display data, which will be transmitted to the display driver, in response to the adjusted synchronization signal.

Abstract: A display controller comprises a merger and an alpha blender. The merger is configured to mix a first left frame comprising first left pixel data and a first right frame comprising first right pixel data based on a three-dimensional (3D) display format, and further configured and to output a first mixed frame and a second mixed frame. The alpha blender is configured to blend the first mixed frame and the second mixed frame to produce a first blended frame.

Abstract: A system-on-chip (SoC), an electronic system including the same, and a method of operating the same are provided. The method includes setting real-time information indicating whether a master block is a real-time block in a real-time information register of the master block. A weight is set in a weight register of the master block. Buffer information of the master block is checked. A quality-of-service (QoS) signal is generated using the buffer information and the weight. A priority of the master block to use the bus is determined based on the QoS signal.

Abstract: An image display system includes: a frame buffer including plurality of lines; a memory controller conducting writing and reading operations with the frame buffer; an image data provider supplying image data to the memory controller and generating a writing address; a display controller generating a reading address and receiving image data that is read from the frame buffer by the memory controller; a tearing-protection bus arbiter storing a burst length, receiving the writing and reading addresses, and selectively outputting the writing and reading addresses; and a display device displaying the image data by the display controller. The reading address contains a start address for the reading operation and the writing address contains a start address for the writing operation.

Abstract: A scaler is provided and includes filters each receiving input pixel data and scaling the input pixel data using a scaling factor to generate a scaled pixel value, and a plurality of mixers, less than the plurality of filters. A first mixer performs a first blending operation on a first scaled pixel value and a second scaled pixel value provided by different filters. A second mixer performs a second blending operation on the blended result of the first mixer and a third scaled pixel value provided by anther filter.

Abstract: A display controller can include a blending coefficient storing unit and an image mixing unit. The blending coefficient storing unit can store blending coefficients. The image mixing unit can receive left-eye image data and right-eye image data, and generate three-dimensional image data by performing a blending operation on the left-eye image data and the right-eye image data using the blending coefficients stored in the blending coefficient storing unit.

Abstract: An image processing device includes a first image enhancer and a second image enhancer. The first image enhancer receives first image data and generates first image enhancement information by analyzing the first image data. The second image enhancer receives second image data and generates second image enhancement information by analyzing the second image data. The first image enhancer converts the first image data into first enhanced image data based on the first image enhancement information and the second image enhancement information. The second image enhancer converts the second image data into second enhanced image data based on the first image enhancement information and the second image enhancement information.

Abstract: An under-run compensation circuit is provided. The under-run compensation circuit is configured to receive a clock signal, data, and an under-run detection signal that indicates whether or not an under-run is occurring. The under-run compensation circuit is further configured to output the clock signal and the data when receiving the under-run detection signal that indicates that an under-run is not occurring. The under-run compensation circuit is additionally configured to output the clock signal and dummy data when receiving the under- run detection signal that indicates that an under-run is occurring.

Abstract: Provided are an interconnect, a bus system with interconnect, and bus system operating method. The bus system includes a master, slaves access by the master, and an interconnect. The interconnect connects the master with the slaves in response to selection bits identified in a master address provided by the master.

Abstract: The display controller includes a decoder, a control circuit, and a video output logic circuit. The decoder is configured to decode a first display command and output a decoding signal and first synchronizing information indicating the first display command is received. The control circuit is configured to generate a first control signal based on second synchronizing information and the decoding signal. The second synchronizing information is output from a second display controller and indicates a second display command is received. The video output logic circuit is configured to send a part of video data stored in a video source and a plurality of first timing control signals for displaying the part of the video data on a display to the display based on the first control signal.

Abstract: Multi-processor systems and methods thereof are provided. In an example, the multi-processor system may include a boot memory including a plurality of boot codes, each of the plurality of boot codes configured to facilitate an initialization process at one of a plurality of intellectual property (IP) blocks, each of the plurality of IP blocks having shared access to the boot memory. In another example, the multi-processor system may receive, from a first processor, a request to provide one of a plurality of boot codes from a boot memory, the received request sent in response to a system initializing signal, may read the requested boot code from the boot memory and may transfer, from a second processor, the read boot code to the first processor.

Abstract: A camera module includes an image sensor configured to convert an optical signal received through a lens into an electrical signal and generate full-size image data, an image signal processing unit configured to calibrate and output the full-size image data, a first memory unit configured to periodically receive and store the full-size image data from the image signal processing unit, a scaling unit configured to scale down the full-size image data received from the first memory unit and periodically output scaled-down image data to a display device, and an encoder configured to receive the full-size image data stored in the first memory unit, convert it into a compressed file in a predetermined format, and output the compressed file upon opening of a shutter.

Abstract: An image processor includes a rotation block and a scaler which share a line buffer block with each other. The image processor receives rearranged pixel data from a memory unit based on rotation information for generating a rotated image and performs scaling on the rearranged pixel data.

Abstract: Multi-processor systems and methods thereof are provided. In an example, the multi-processor system may include a boot memory including a plurality of boot codes, each of the plurality of boot codes configured to facilitate an initialization process at one of a plurality of intellectual property (IP) blocks, each of the plurality of IP blocks having shared access to the boot memory. In another example, the multi-processor system may receive, from a first processor, a request to provide one of a plurality of boot codes from a boot memory, the received request sent in response to a system initializing signal, may read the requested boot code from the boot memory and may transfer, from a second processor, the read boot code to the first processor.