Abstract: An integrated circuit having a vertical transistor includes first through fourth gate lines extending in a first direction and sequentially arranged in parallel with each other, a first top active region over the first through third gate lines and insulated from the second gate line, and a second top active region. The first top active region forms first and third transistors with the first and third gate lines respectively. The second top active region is over the second through fourth gate lines and insulated from the third gate line. The second top active region forms second and fourth transistors with the second and fourth gate lines respectively.

Abstract: An integrated circuit includes: a lower layer including first and second lower patterns extending in a first direction; a first via arranged on the first lower pattern, and a second via arranged on the second lower pattern; a first upper pattern arranged on the first via; and a second upper pattern arranged on the second via, a first color is assigned to the first upper pattern, a second color is assigned to the second upper pattern, the first and second upper patterns are adjacent to each other in a second direction, and the first via is arranged in a first edge region of the first lower pattern, the first edge region being farther away from the second lower pattern than a second edge region of the first lower pattern, the second edge region being opposite to the first edge region.

Abstract: In one embodiment, the standard cell includes first and second active regions defining an intermediate region between the first and second active regions; and first, second and third gate lines crossing the first and second active regions and crossing the intermediate region. The first gate line is divided into an upper first gate line and a lower first gate line by a first gap insulating layer in the intermediate region, the second gate line is undivided, and the third gate line is divided into an upper third gate line and a lower third gate line by a second gap insulating layer in the intermediate region.

Abstract: An integrated circuit includes a standard cell. The standard cell may include a plurality of gate lines and a plurality of first wirings. The plurality of first wirings may include a clubfoot structure conductive pattern that includes a first conductive pattern and a second conductive pattern spaced apart from each other. Each of the first conductive pattern and the second conductive pattern may include a first line pattern extending in a first direction and a second line pattern protruding from one end of the first line pattern in a direction perpendicular to the first direction. The plurality of gate lines may be spaced apart from each other by a first pitch in the first direction, and the plurality of second wirings may be spaced apart from each other by a second pitch in the first direction. The first pitch may be greater than the second pitch.

Abstract: An integrated circuit includes: a lower layer including first and second lower patterns extending in a first direction; a first via arranged on the first lower pattern, and a second via arranged on the second lower pattern; a first upper pattern arranged on the first via; and a second upper pattern arranged on the second via, a first color is assigned to the first upper pattern, a second color is assigned to the second upper pattern, the first and second upper patterns are adjacent to each other in a second direction, and the first via is arranged in a first edge region of the first lower pattern, the first edge region being farther away from the second lower pattern than a second edge region of the first lower pattern, the second edge region being opposite to the first edge region.

Abstract: A standard cell of an IC includes a cell area including a transistor configured to determine a function of the standard cell; a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in a first direction; and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. The active area includes a first active area and a second active area spaced apart from each other in a second direction perpendicular to the first direction and extend parallel to each other in the first direction. At least one of the first active area and the second active area provided in the first dummy area is biased, and at least one of the first active area and the second active area provided in the second dummy area is biased.

Abstract: An integrated circuit includes first and second active regions extending in a first direction, a first gate line extending in a second direction substantially perpendicular to the first direction and crossing the first and second active regions, and a first contact jumper including a first conductive pattern intersecting the first gate line above the first active region and a second conductive pattern extending in the second direction above the first gate line and connected to the first conductive pattern.

Abstract: A display apparatus includes a display panel including pixels arranged at an intersection of data lines and gate lines, a source driver IC configured to be disposed on one side surface of the display panel to apply a data voltage to the data lines, a gate driver IC configured to be disposed on any one of two side surfaces which are adjacent to the one side surface of the display panel to apply a gate driving voltage to the gate lines, and a controller configured to receive feedback on a gate driving voltage applied to at least one pixel, detect a distortion of the gate driving voltage applied to the pixel based on the feedback, adjust a level of the gate driving voltage applied to the gate lines to compensate for the distortion of the gate driving voltage, and apply the adjusted gate driving voltage to the gate lines.

Abstract: An integrated circuit (IC) may include a plurality of standard cells. At least one standard cell of the plurality of standard cells may include a power rail configured to supply power to the at least one standard cell, the power rail extending in a first direction, a cell area including at least one transistor configured to determine a function of the at least one standard cell, a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in the first direction, and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. A region of the active area, which is included in the first dummy area or the second dummy area, is electrically connected to the power rail.

Abstract: A light emitting diode (LED) apparatus is provided. The LED apparatus includes a light emitting diode, a light conversion layer stacked on the light emitting diode and configured to convert a wavelength of light incident from the light emitting diode, a reflection coating layer stacked on the light conversion layer and configured to pass the light of which the wavelength is converted in light incident from the light conversion layer therethrough and reflecting the other light, and a color filter stacked on the reflection coating layer and configured to correspond to the light conversion layer.

Abstract: An integrated circuit may include a first active region and a second active region, and the first and second active regions may extend on a substrate in a first horizontal direction in parallel to each other and have different conductivity types from each other. A first gate line may extend in a second horizontal direction crossing the first horizontal direction, and may form a first transistor with the first active region. The first transistor may include a gate to which a first input signal is applied. The first gate line may include a first partial gate line that overlaps the first active region in a perpendicular direction and that has an end on a region between the first and second active regions.

Abstract: An integrated circuit includes first and second active regions extending in a first direction, a first gate line extending in a second direction substantially perpendicular to the first direction and crossing the first and second active regions, and a first contact jumper including a first conductive pattern intersecting the first gate line above the first active region and a second conductive pattern extending in the second direction above the first gate line and connected to the first conductive pattern.

Abstract: A light emitting diode (LED) apparatus is provided. The LED apparatus includes a light emitting diode, a light conversion layer stacked on the light emitting diode and configured to convert a wavelength of light incident from the light emitting diode, a reflection coating layer stacked on the light conversion layer and configured to pass the light of which the wavelength is converted in light incident from the light conversion layer therethrough and reflecting the other light, and a color filter stacked on the reflection coating layer and configured to correspond to the light conversion layer.

Abstract: An LED apparatus is provided. The LED apparatus includes a plurality of substrate layers, each substrate layer corresponding to one of a plurality of sub-pixels of a pixel; a heat sink plate provided on a first side of each substrate layer, the heat sink plate including a patterned area provided between adjacent substrate layers of the plurality of substrates layers; a fluorescence provided on the heat sink plate overlapping at least a portion of one of the plurality of substrate layers; and a plurality of light emitting diodes, each light emitting diode formed on a second side opposite to the first side of each substrate layer.

Abstract: A display module is provided including a pixel region having a plurality of pixels and a black matrix arranged outside the pixel region. Each of the pixels is separated from adjacent pixels by a first interval, a left distance from the left edge to a first one of the plurality of pixels plus a right distance from a second one of the plurality of pixels to the right edge is a first distance, and a bottom distance from the bottom edge to a third one of the plurality of pixels plus a top distance from a fourth one of the plurality of pixels to the top edge is the first distance.

Abstract: According to an exemplary embodiment of the present inventive concept, a semiconductor device is provided as follows. An active region is disposed in one side of a gate line. A non-active region is disposed in the other side of the gate line. A jumper pattern crosses a top portion of the gate line, overlapping the active region and the non-active region. A boundary between the active region and the non-active region is underneath the gate line.

Abstract: Provided is an integrated circuit including a plurality of standard cells each including a front-end-of-line (FEOL) region and a back-end-of-line (BEOL) region on the FEOL region, the FEOL region including at least one gate line extending in a first horizontal direction. A BEOL region of a first standard cell among the plurality of standard cells includes an eaves section not overlapping an FEOL region of the first standard cell in a vertical direction, the eaves section protruding in a second horizontal direction perpendicular to the first horizontal direction.

Abstract: Provided are a wafer probe card that matches in one-to-one correspondence with an LED wafer by implementing a probe system having the same size as the LED wafer, and inspects brightness and wavelength of light emitted from a plurality of LEDs provided on the LED wafer at once by controlling the plurality of LEDs to emit light, an analysis apparatus including the same, and a method of fabricating the wafer probe card.

Abstract: An LED display module, a display apparatus, and a method for controlling the LED display module and the display apparatus are provided. The LED display module includes a plurality of first LEDs arranged in a first line and a plurality of second LEDs arranged in a second line; a plurality of source interfaces, each of which is commonly connected to an anode of a corresponding one of the plurality of first LEDs and a cathode of a corresponding one of the plurality of second LEDs arranged in the same column as the corresponding one of the plurality of first LEDs; and a gate interface commonly connected to a cathode of each of the plurality of the first LEDs and an anode of each of the plurality of the second LEDs.

Abstract: An integrated circuit including: a power rail including first and second conductive lines spaced apart from each other in a vertical direction, wherein the first and second conductive lines extend in parallel to each other in a first horizontal direction, and are electrically connected to each other, to supply power to a first standard cell, wherein the first and second conductive lines are disposed at a boundary of the first standard cell; and a third conductive line between the first and second conductive lines and extending in a second horizontal direction orthogonal to the first horizontal direction, to transfer an input signal or an output signal of the first standard cell.