Abstract: An integrated circuit including: a power rail including first and second conductive lines spaced apart from each other in a vertical direction, wherein the first and second conductive lines extend in parallel to each other in a first horizontal direction, and are electrically connected to each other, to supply power to a first standard cell, wherein the first and second conductive lines are disposed at a boundary of the first standard cell; and a third conductive line between the first and second conductive lines and extending in a second horizontal direction orthogonal to the first horizontal direction, to transfer an input signal or an output signal of the first standard cell.

Abstract: An LED display module, a display apparatus, and a method for controlling the LED display module and the display apparatus are provided. The LED display module includes a plurality of first LEDs arranged in a first line and a plurality of second LEDs arranged in a second line; a plurality of source interfaces, each of which is commonly connected to an anode of a corresponding one of the plurality of first LEDs and a cathode of a corresponding one of the plurality of second LEDs arranged in the same column as the corresponding one of the plurality of first LEDs; and a gate interface commonly connected to a cathode of each of the plurality of the first LEDs and an anode of each of the plurality of the second LEDs.

Abstract: A light emitting diode (LED) apparatus is provided. The LED apparatus includes a light emitting diode, a light conversion layer stacked on the light emitting diode and configured to convert a wavelength of light incident from the light emitting diode, a reflection coating layer stacked on the light conversion layer and configured to pass the light of which the wavelength is converted in light incident from the light conversion layer therethrough and reflecting the other light, and a color filter stacked on the reflection coating layer and configured to correspond to the light conversion layer.

Abstract: An integrated circuit includes first and second active regions extending in a first direction, a first gate line extending in a second direction substantially perpendicular to the first direction and crossing the first and second active regions, and a first contact jumper including a first conductive pattern intersecting the first gate line above the first active region and a second conductive pattern extending in the second direction above the first gate line and connected to the first conductive pattern.

Abstract: An integrated circuit (IC) may include a plurality of standard cells. At least one standard cell of the plurality of standard cells may include a power rail configured to supply power to the at least one standard cell, the power rail extending in a first direction, a cell area including at least one transistor configured to determine a function of the at least one standard cell, a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in the first direction, and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. A region of the active area, which is included in the first dummy area or the second dummy area, is electrically connected to the power rail.

Abstract: An integrated circuit having a vertical transistor includes first through fourth gate lines extending in a first direction and sequentially arranged in parallel with each other, a first top active region over the first through third gate lines and insulated from the second gate line, and a second top active region. The first top active region forms first and third transistors with the first and third gate lines respectively. The second top active region is over the second through fourth gate lines and insulated from the third gate line. The second top active region forms second and fourth transistors with the second and fourth gate lines respectively.

Abstract: An integrated circuit includes: a lower layer including first and second lower patterns extending in a first direction; a first via arranged on the first lower pattern, and a second via arranged on the second lower pattern; a first upper pattern arranged on the first via; and a second upper pattern arranged on the second via, a first color is assigned to the first upper pattern, a second color is assigned to the second upper pattern, the first and second upper patterns are adjacent to each other in a second direction, and the first via is arranged in a first edge region of the first lower pattern, the first edge region being farther away from the second lower pattern than a second edge region of the first lower pattern, the second edge region being opposite to the first edge region.

Abstract: In one embodiment, the standard cell includes first and second active regions defining an intermediate region between the first and second active regions; and first, second and third gate lines crossing the first and second active regions and crossing the intermediate region. The first gate line is divided into an upper first gate line and a lower first gate line by a first gap insulating layer in the intermediate region, the second gate line is undivided, and the third gate line is divided into an upper third gate line and a lower third gate line by a second gap insulating layer in the intermediate region.

Abstract: A memory device includes a memory cell array including a plurality of memory cells, a plurality of word lines connected to the plurality of memory cells, a plurality of bit lines connected to the plurality of memory cells, a plurality of complementary bit lines connected to the plurality of memory cells, a plurality of auxiliary bit lines, a plurality of auxiliary complementary bit lines, and a switch circuit. The switch circuit electrically connects the plurality of auxiliary bit lines to the plurality of bit lines during a write operation, electrically connects the plurality of auxiliary complementary bit lines to the plurality of complementary bit lines during the write operation, electrically disconnects the plurality of auxiliary bit lines from the plurality of bit lines during a read operation, and electrically disconnects the plurality of auxiliary complementary bit lines from the plurality of complementary bit lines during the read operation.

Abstract: A light emitting diode (LED) panel and a manufacturing method thereof are provided. The LED panel includes: a substrate; and a plurality of subpixel areas formed over a substrate, in which each of the plurality of subpixel areas include: a plurality of pixel electrodes spaced from each other; at least LED formed over the plurality of pixel electrodes; and at least one transistor disposed at one side of at least one of the plurality of pixel electrodes to control at least one of the plurality of pixel electrodes.

Abstract: A semiconductor device is provided as follows. An active region extends along a first direction. A gate line overlaps the active region and extending along a second direction intersecting the first direction. A power rail has a main pattern extending along the first direction and a sub-pattern branching off from the main pattern to extend along the second direction. A first source/drain contact, electrically connected to the power rail, overlaps the active region and the sub-pattern.

Abstract: A memory device includes a memory cell array including a plurality of memory cells, a plurality of word lines connected to the plurality of memory cells, a plurality of bit lines connected to the plurality of memory cells, a plurality of complementary bit lines connected to the plurality of memory cells, a plurality of auxiliary bit lines, a plurality of auxiliary complementary bit lines, and a switch circuit. The switch circuit electrically connects the plurality of auxiliary bit lines to the plurality of bit lines during a write operation, electrically connects the plurality of auxiliary complementary bit lines to the plurality of complementary hit lines during the write operation, electrically disconnects the plurality of auxiliary bit lines from the plurality of bit lines during a read operation, and electrically disconnects the plurality of auxiliary complementary bit lines from the plurality of complementary bit lines during the read operation.

Abstract: Disclosed is a novel compound to function as a calcium-dependent chloride channel blocking agent.

Abstract: A semiconductor device is provided. The semiconductor device includes an active region, a gate line, a first metal interconnect, a power rail, and a second metal interconnect. The gate line overlaps the active region and extends along a first direction. The first metal interconnect overlaps the active region and the gate line. The first metal interconnect extends along a second direction intersecting the first direction. The power rail is disposed in a higher layer than the first metal interconnect. The power rail extends along the second direction. The second metal interconnect is disposed in a same layer as the power rail, the second metal interconnect extends along the second direction.

Abstract: An LED display module, a display apparatus, and a method for controlling the LED display module and the display apparatus are provided. The LED display module includes a plurality of first LEDs arranged in a first line and a plurality of second LEDs arranged in a second line; a plurality of source interfaces, each of which is commonly connected to an anode of a corresponding one of the plurality of first LEDs and a cathode of a corresponding one of the plurality of second LEDs arranged in the same column as the corresponding one of the plurality of first LEDs; and a gate interface commonly connected to a cathode of each of the plurality of the first LEDs and an anode of each of the plurality of the second LEDs.

Abstract: An LED apparatus is provided. The LED apparatus includes a plurality of substrate layers, each substrate layer corresponding to one of a plurality of sub-pixels of a pixel; a heat sink plate provided on a first side of each substrate layer, the heat sink plate including a patterned area provided between adjacent substrate layers of the plurality of substrates layers; a fluorescence provided on the heat sink plate overlapping at least a portion of one of the plurality of substrate layers; and a plurality of light emitting diodes, each light emitting diode formed on a second side opposite to the first side of each substrate layer.

Abstract: A backlight unit is provided. The backlight unit includes: a first surface light source array; a second surface light source array disposed on an upper portion of the first surface light source array and arranged such that a light emitting surface of the second surface light source array is parallel with a light emitting surface of the first surface light source array; and a reflection plate disposed on a lower portion of the first surface light source array and arranged such that a reflective surface of the reflection plate is parallel with the light emitting surface of the first surface light source array, wherein the second surface light source array is stacked on the first surface light source array such that the first and second surface light source arrays are offset from each other in a plane parallel to the light emitting surfaces.

Abstract: A tiled display includes a plurality of bezelless liquid crystal display (LCD) panels in which pixels are exposed from at least one of a top side, a bottom side, a left side, and a right side thereof; at least one backlight unit disposed below the plurality of bezelless LCD panels and configured to emit light. The plurality of bezelless LCD panels are disposed such that sides from which the pixels are exposed are connected to each other, the backlight unit comprises a plurality of light emitting diodes (LEDs) configured to emit the light to the bezelless LCD panel, and the plurality of LEDs are disposed at equal intervals below the plurality of bezelless LCD panels including a portion where the plurality of bezelless LCD panels are connected to each other.

Abstract: According to an exemplary embodiment of the present inventive concept, a semiconductor device is provided as follows. An active region is disposed in one side of a gate line. A non-active region is disposed in the other side of the gate line. A jumper pattern crosses a top portion of the gate line, overlapping the active region and the non-active region. A boundary between the active region and the non-active region is underneath the gate line.

Abstract: A semiconductor device is provided as follows. An active region extends along a first direction. A gate line overlaps the active region and extending along a second direction intersecting the first direction. A power rail has a main pattern extending along the first direction and a sub-pattern branching off from the main pattern to extend along the second direction. A first source/drain contact, electrically connected to the power rail, overlaps the active region and the sub-pattern.