Abstract: The present invention relates to an automatic real-time quantitative amplification system which can perform analysis of various biological samples, and more particularly to an automatic real-time quantitative amplification system in which a plurality of decks for respectively accommodating biological samples are put in a deck storing/transferring device, whereby it is possible to automatically analyze an amount or existence of a target substance containing a target nucleic acid in the biologic sample, such as a particular gene, a particular, a particular pathogenic bacterium and a particular protein, by amplifying the target nucleic acid purified by some processes of purification, purification after culture, or purification after reaction of the target substance contained in the biological sample and then checking an amount of the amplified target nucleic acid.

Abstract: There is provided a structure and a method of manufacturing a semiconductor package. The method includes disposing a first semiconductor device and through mold ball connectors (TMBCs) on a first surface of an interconnection structure layer, recessing a molding layer on the first surface of the interconnection structure layer to expose a portion of each of the TMBCs, attaching outer connectors to the exposed portions of the TMBCs, and mounting a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer.

Abstract: There may be provided a method of manufacturing a semiconductor package. The method may include disposing a first semiconductor device and through mold ball connectors (TMBCs) on a first surface of an interconnection structure layer, forming a molding layer on the first surface of the interconnection structure layer to expose a portion of each of the TMBCs, attaching outer connectors to the exposed portions of the TMBCs, mounting a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer, and attaching a heat spreader to the second surface of the interconnection structure layer to overlap with a portion of the first semiconductor device.

Abstract: There may be provided a method of manufacturing a semiconductor package. The method may include disposing a first semiconductor device and through mold ball connectors (TMBCs) on a first surface of an interconnection structure layer, forming a molding layer on the first surface of the interconnection structure layer to expose a portion of each of the TMBCs, attaching outer connectors to the exposed portions of the TMBCs, mounting a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer, and attaching a heat spreader to the second surface of the interconnection structure layer to overlap with a portion of the first semiconductor device.

Abstract: Wafer level packages are provided. The wafer level package includes alignment marks disposed at a first surface of a protection wafer, a semiconductor die disposed on the first surface of the protection wafer to be spaced apart from the alignment marks, a first photosensitive dielectric layer covering the semiconductor die and having a flat top surface, and a second dielectric layer covering the flat top surface of the first photosensitive dielectric layer. Redistribution lines are disposed between the first photosensitive dielectric layer and the second dielectric layer and electrically connected to the semiconductor die through first opening portions penetrating the first photosensitive dielectric layer. Outer connectors are disposed on the second dielectric layer and electrically connected to the redistribution lines through second opening portions penetrating the second dielectric layer.

Abstract: There is provided a structure and a method of manufacturing a semiconductor package. The method includes disposing a first semiconductor device and through mold ball connectors (TMBCs) on a first surface of an interconnection structure layer, recessing a molding layer on the first surface of the interconnection structure layer to expose a portion of each of the TMBCs, attaching outer connectors to the exposed portions of the TMBCs, and mounting a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer.

Abstract: A semiconductor package includes first bump pads on a first surface of an interconnection structure layer, elevated pads thicker than the first bump pads on the first surface of the interconnection structure layer, a first semiconductor device connected on the first bump pads, through mold ball connectors connected on the elevated pads, respectively, a molding layer disposed covering the first surface of the interconnection structure layer to expose a portion of each of the through mold ball connectors, outer connectors respectively attached to the through mold ball connectors, and a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer.

Abstract: A semiconductor package includes an extendible molding member, a chip embedded in the molding member to have a warped shape, and connectors disposed in the molding member. First surfaces of the connectors are exposed at a surface of the molding member, and second surfaces of the connectors are coupled to the chip.

Abstract: A novel substituted N-(pyrrolidin-3-yl)-7H-pyrrolo[2,3-d]pyrimidin-4-amine and a use thereof as a Janus kinase (JAK) inhibitor are provided.

Abstract: Systems and methods to detect, quantify, and control process-induced asymmetric signatures using patterned wafer geometry measurements are disclosed. The system may include a geometry measurement tool configured to obtain a first set of wafer geometry measurements of the wafer prior to the wafer undergoing a fabrication process and to obtain a second set of wafer geometry measurements of the wafer after the fabrication process. The system may also include a processor in communication with the geometry measurement tool. The processor may be configured to: calculate a geometry-change map based on the first set of wafer geometry measurements and the second set of wafer geometry measurements; analyze the geometry-change map to detect an asymmetric component induced to wafer geometry by the fabrication process; and estimate an asymmetric overlay error induced by the fabrication process based on the asymmetric component detected in wafer geometry.

Abstract: A semiconductor package may include a first semiconductor chip, second semiconductor chips disposed to respectively overlap with portions of the first semiconductor chip, a interposer disposed to overlap with a portion of the first semiconductor chip, and a package substrate disposed on backside surfaces of the second semiconductor chips opposite to the first semiconductor chip. The interposer may be disposed between the first semiconductor chip and the package substrate. First conductive coupling members connect the first semiconductor chip to the second semiconductor chips. Second conductive coupling members connect the first semiconductor chip to the interposer. Third conductive coupling members connect the interposer to the package substrate.

Abstract: A semiconductor package structure and a method for manufacturing the same are provided. According to the method, a first mold layer is formed to cover a first semiconductor chip and a first bumps. A portion of the first mold layer is removed to expose top portions of the first bumps and second bumps are disposed to be connected to each of the first bumps. A second mold layer is formed, and the second mold layer is recessed to form through mold connectors that substantially penetrate the second mold layer with the second bumps disposed on the first bumps.

Abstract: A display apparatus having a screen on which recording by a user's touch can be performed is provided. The display apparatus includes a display configured to provide the screen, an accommodator configured to accommodate the display and having a screen aperture formed thereon with a predetermined depth to expose the screen, a touch position sensor configured to sense the position of a touch device that is used by a user when a distance between the screen and the touch device is shorter than the predetermined depth, a vibration sensor mounted on the display and configured to sense vibration of the display due to a contact of the touch device with the screen, and a controller configured to control the display to perform recording on a point of the screen that corresponds to the sensed position of the touch device when the vibration is sensed.

Abstract: Semiconductor devices are provided. The semiconductor device includes a semiconductor layer having a first surface and a second surface that are opposite each other, a through electrode penetrating the semiconductor layer and having a protrusion that protrudes over the second surface of the semiconductor layer, a front-side bump disposed over the first surface of the semiconductor layer and electrically coupled to the through electrode, a polymer pattern disposed over the second surface of the semiconductor layer to enclose a part of the protrusion of the through electrode, and a back-side bump covering an upper surface and a sidewall of a remaining part of the protrusion of the through electrode and extending over a portion of the polymer pattern.

Abstract: A manufacturing method for a semiconductor device includes forming a first stacked structure, forming a first hole penetrating the first stacked structure, forming a reflective metal pattern in the first hole, filling an etch stop layer in the first hole and over the reflective metal pattern, forming a second stacked structure over the first stacked structure, and forming a second hole penetrating the second stacked structure to expose the etch stop layer.

Abstract: According to various embodiments, there may be provided packages, semiconductors, and wafer level packages, and there may be provided methods of manufacturing packages, semiconductors, and wafer level packages. A method of manufacturing a wafer level package may include forming alignment marks at a surface of a protection wafer, mounting semiconductor dice on the protection wafer using the alignment marks, forming a first dielectric layer covering the semiconductor dice, planarizing a top surface of the first photosensitive layer, exposuring and developing portions of the planarized first dielectric layer to form opening portions exposing portions of the semiconductor dice, and forming redistribution lines on the first photosensitive dielectric layer. A second dielectric layer may be formed to cover the redistribution lines. Related wafer level packages may also be provided.

Abstract: Disclosed are a multilayer ceramic condenser and a method for manufacturing the same. There is provided a multilayer ceramic condenser including: a multilayer main body in which a plurality of dielectric layers including a first side, a second side, a third side, and a fourth side are stacked; a first cover layer and a second cover layer forming the plurality of dielectric layers; a first dielectric layer disposed between the first cover layer and the second cover layer and printed with a first inner electrode pattern drawn to the first side; a second dielectric layer alternately stacked with the first dielectric layer and printed with a second inner electrode pattern drawn to the third side; and a first side portion and a second side portion each formed on the second side and the fourth side opposite to each other.

Abstract: A semiconductor package includes an extendible molding member, a chip embedded in the molding member to have a warped shape, and connectors disposed in the molding member. First surfaces of the connectors are exposed at a surface of the molding member, and second surfaces of the connectors are coupled to the chip.

Abstract: A semiconductor package structure and a method for manufacturing the same are provided. According to the method, a first mold layer is formed to cover a first semiconductor chip and a first bumps. A portion of the first mold layer is removed to expose top portions of the first bumps and second bumps are disposed to be connected to each of the first bumps. A second mold layer is formed, and the second mold layer is recessed to form through mold connectors that substantially penetrate the second mold layer with the second bumps disposed on the first bumps.

Abstract: In an embodiment of the present disclosure, a method of manufacturing a semiconductor device may include forming a pattern group on a substrate, the substrate being divided into first and second regions, each pattern including a silicon layer, forming an insulating pattern on the substrate, the insulating pattern partially exposing the silicon layer on the first region and blocking the silicon layer on the second region, converting the exposed silicon layer on the first region to a silicide layer while the blocked silicon layer on the second region is protected from the conversion, and performing a subsequent process using, as an overlay vernier, at least a portion of the pattern group formed on the second region.