Abstract: A semiconductor memory device and method thereof are provided. The example method may be directed to performing a memory operation in a semiconductor memory device, and may include receiving data and a data masking signal corresponding to at least a portion of the received data, the received data scheduled to be written into memory in response to a write command and the data masking signal configured to block the at least a portion of the received data from being written into the memory and configuring timing parameters differently for each of the received data and the data masking signal so as to execute the write command without writing the at least a portion of the received data into the memory.

Abstract: A semiconductor memory device is provided. The device includes an on die termination circuit controlling a termination resistance value by detecting a phase change of a signal inputted through a pad. Additionally, the on die termination circuit changes the termination resistance value when an identical phase signal is inputted during n (n is positive integer) periods of a clock signal.

Abstract: A row active time control circuit is described that includes a master signal generating circuit and a row active control signal generating circuit. The master signal generating circuit generates one or more row active master signals based on an active command signal, a pre-charge command signal, and one or more row active control signals. The row active control signal generating circuit generates a pulse signal that oscillates based on the one or more row active master signals. The row active control signal also generates the one or more row active control signals by dividing a frequency of the generated pulse signal.

Abstract: A semiconductor memory device and method directed to performing a memory operation in a semiconductor memory device, which include receiving data and a data masking signal corresponding to a portion of the received data configured to be written into memory in response to a write command and the data masking signal configured to block the at least a portion of the received data from being written into the memory, and further configuring different timing parameters of the received data and the data masking signal for executing the write command without writing the at least a portion of the received data into the memory.

Abstract: There are provided a semiconductor memory device and a burn-in test method thereof. A semiconductor memory device according to an aspect of the invention includes a plurality of memory cell blocks, each of which includes a plurality of memory cells that are respectively coupled to a plurality of word lines and a plurality of bit lines, a word line control unit activating word lines in memory cell blocks that correspond to row address signals and word lines in memory cell blocks that do not correspond to the row address signals, during a test operation, and a write circuit writing data in the memory cell blocks that correspond to the row address signals and not writing data in the memory cell blocks that do not correspond to the row address signals, during the test operation.

Abstract: Provided is a semiconductor memory device and method that can control internal supply voltages independently. The semiconductor memory device includes a memory cell array, a reference voltage generating unit, an internal reference voltage generating unit, and an internal supply voltage generating unit. The reference voltage generating unit outputs a reference voltage in response to an external voltage. The internal reference voltage generating unit converts the reference voltage into a plurality of internal reference voltages, and outputs the plurality of internal reference voltages. The internal supply voltage generating unit converts the plurality of internal reference voltages into a plurality of internal supply voltages, and outputs the plurality of internal supply voltages. A first internal reference voltage is used to generate a first internal supply voltage and a second internal reference voltage is used to generate a second internal supply voltage.

Abstract: A probe sensing pad used to detect a position of a probe needle includes a probe area, at least two sensing regions contacting peripheral portions of the probe area, sensing elements of different electrical characteristics connected to corresponding sensing regions, and at least one isolation region for electrically insulting the sensing regions. The position of the probe needle relative to the probe sensing pad may be rapidly detected and automatically corrected toward a desired contact site of the probe sensing pad depending upon the voltage measured by a probe needle contacting the probe sensing pad. That is, the measured voltage will have a first value if deflected in a first direction, a second value (different from the first) if deflected in a second direction, and so on. The position of the probe needle can be corrected based on this measurement.

Abstract: An input/output sense amplifier (IOSA) controller of a semiconductor memory device includes an auto pulse generator and a latch enable signal generating circuit. The auto pulse generator generates an auto pulse signal having a first pulse shape. The latch enable signal generating circuit generates a first latch enable signal having a second pulse shape in response to an auto pulse signal in normal mode, and generates a second latch enable signal having a level shape that is enabled for long duration in response to the write enable bar signal in test mode. Accordingly, the semiconductor memory device including the IOSA controller may safely test a characteristic of the IOSA.

Abstract: A row active time control circuit is described that includes a master signal generating circuit and a row active control signal generating circuit. The master signal generating circuit generates one or more row active master signals based on an active command signal, a pre-charge command signal, and one or more row active control signals. The row active control signal generating circuit generates a pulse signal that oscillates based on the one or more row active master signals. The row active control signal also generates the one or more row active control signals by dividing a frequency of the generated pulse signal.

Abstract: A semiconductor memory device includes a memory core unit, N data output buffers, N data output ports, and a plurality of test logic circuits. The memory core unit stores test data through N data lines. The N data output buffers are respectively connected to the corresponding N data lines. The N data output ports are connected to the corresponding N data output buffers, and exchange the test data with an external tester respectively. The plurality of test logic circuits receives the test data through the K data lines from the N data lines, performs test logic operation on the received test data, and provides a data output buffer control signal that determines activation of K data output buffers of the N data output buffers in test mode. The semiconductor memory device reduces test cycle.

Abstract: A bit line sense amplifier circuit for use in a semiconductor memory device, and a control method thereof, in which the bit line sense amplifier circuit is controlled to maintain a precharge state thereof until a sense amplifier enable signal to enable the sense amplifier circuit is applied, thereby preventing the bit line sense amplifier circuit of the semiconductor memory device from floating, and preventing or substantially reducing a coupling effect, thereby providing a precise data sensing and amplification operation.

Abstract: A bit line sense amplifier and method thereof are provided. The example bit line sense amplifier may include a sense amplifying circuit coupled between a first bit line and a second bit line. The sense amplifying circuit may be configured to amplify a voltage difference between the first bit line and the second bit line. The example bit line sense amplifier may further include a power supply voltage providing circuit configured to provide a first power supply voltage and a second power supply voltage to the sense amplifying circuit in response to first and second bit line sensing control signals. The bit line sense amplifier may further include a bit line voltage compensation circuit configured to prevent a voltage-reduction at the first bit line and the second bit line for a delay period, the delay period including at least a period of time after a pre-charging of the first and second bit lines, in response to one or more of the first and second bit line sensing control signals.

Abstract: Provided is a semiconductor memory device. The semiconductor memory device includes: a memory cell array including regular cells; a redundancy memory cell array including redundancy cells for substituting for defective regular cells; a command decoder for generating an operation mode selection signal in response to command signals; a redundancy cell test controller for generating a test operation control signal and transmitting address signals in response to the operation mode selection signal; and a redundancy decoder for decoding the address signals to select the redundancy cells in response to the test operation control signal. All redundancy cells can be selected and tested based on the external command signal and the address signal, and thus it is possible to check all redundancy cells for defects in advance even after the semiconductor memory device is packaged, and to enable only non-defective redundancy cells to be substituted for defective regular cells.

Abstract: Provided is a semiconductor memory device and method that can control internal supply voltages independently. The semiconductor memory device includes a memory cell array, a reference voltage generating unit, an internal reference voltage generating unit, and an internal supply voltage generating unit. The reference voltage generating unit outputs a reference voltage in response to an external voltage. The internal reference voltage generating unit converts the reference voltage into a plurality of internal reference voltages, and outputs the plurality of internal reference voltages. The internal supply voltage generating unit converts the plurality of internal reference voltages into a plurality of internal supply voltages, and outputs the plurality of internal supply voltages. A first internal reference voltage is used to generate a first internal supply voltage and a second internal reference voltage is used to generate a second internal supply voltage.

Abstract: There are provided a semiconductor memory device and a burn-in test method thereof. A semiconductor memory device according to an aspect of the invention includes a plurality of memory cell blocks, each of which includes a plurality of memory cells that are respectively coupled to a plurality of word lines and a plurality of bit lines, a word line control unit activating word lines in memory cell blocks that correspond to row address signals and word lines in memory cell blocks that do not correspond to the row address signals, during a test operation, and a write circuit writing data in the memory cell blocks that correspond to the row address signals and not writing data in the memory cell blocks that do not correspond to the row address signals, during the test operation.

Abstract: An internal supply voltage generation circuit includes first and second driving circuits and a resistive device. The first driving circuit receives a feedback voltage from a first node and generates a first output voltage based on first and second reference voltages to provide the first output voltage to the first node. The first output voltage is maintained between the first and second reference voltages. The second driving circuit receives a feedback voltage from a second node voltage and generates a second output voltage based on third and fourth reference voltages to provide the second output voltage to the second node. The second output voltage is maintained between the third and fourth reference voltages, and the second output voltage of the second node is provided as an internal supply voltage. The resistive device is coupled between the first and second nodes.

Abstract: A semiconductor memory device and method thereof are provided. The example method may be directed to performing a memory operation in a semiconductor memory device, and may include receiving data and a data masking signal corresponding to at least a portion of the received data, the received data scheduled to be written into memory in response to a write command and the data masking signal configured to block the at least a portion of the received data from being written into the memory and configuring timing parameters differently for each of the received data and the data masking signal so as to execute the write command without writing the at least a portion of the received data into the memory.

Abstract: A semiconductor memory device and related test method are disclosed. Test data is defined from a group of M test bits selected from either input data or corresponding output data. A parallel bit test is then conducted on the test data. The M test bits include N test bits, where N is less than M, selected on a bit by bit basis from the output data, and L test bits, where N+L=M, selected from the input data. The selection of input data may be made in accordance with a don't care case for selected test data.

Abstract: An input/output sense amplifier (IOSA) controller of a semiconductor memory device includes an auto pulse generator and a latch enable signal generating circuit. The auto pulse generator generates an auto pulse signal having a first pulse shape. The latch enable signal generating circuit generates a first latch enable signal having a second pulse shape in response to an auto pulse signal in normal mode, and generates a second latch enable signal having a level shape that is enabled for long duration in response to the write enable bar signal in test mode. Accordingly, the semiconductor memory device including the IOSA controller may safely test a characteristic of the IOSA.

Abstract: A probe sensing pad used to detect a position of a probe needle includes a probe area, at least two sensing regions contacting peripheral portions of the probe area, sensing elements of different electrical characteristics connected to corresponding sensing regions, and at least one isolation region for electrically insulting the sensing regions. The position of the probe needle relative to the probe sensing pad may be rapidly detected and automatically corrected toward a desired contact site of the probe sensing pad depending upon the voltage measured by a probe needle contacting the probe sensing pad. That is, the measured voltage will have a first value if deflected in a first direction, a second value (different from the first) if deflected in a second direction, and so on. The position of the probe needle can be corrected based on this measurement.