Abstract: Provided is a semiconductor memory device. The semiconductor memory device includes: a memory cell array including regular cells; a redundancy memory cell array including redundancy cells for substituting for defective regular cells; a command decoder for generating an operation mode selection signal in response to command signals; a redundancy cell test controller for generating a test operation control signal and transmitting address signals in response to the operation mode selection signal; and a redundancy decoder for decoding the address signals to select the redundancy cells in response to the test operation control signal. All redundancy cells can be selected and tested based on the external command signal and the address signal, and thus it is possible to check all redundancy cells for defects in advance even after the semiconductor memory device is packaged, and to enable only non-defective redundancy cells to be substituted for defective regular cells.

Abstract: An internal supply voltage generation circuit includes first and second driving circuits and a resistive device. The first driving circuit receives a feedback voltage from a first node and generates a first output voltage based on first and second reference voltages to provide the first output voltage to the first node. The first output voltage is maintained between the first and second reference voltages. The second driving circuit receives a feedback voltage from a second node voltage and generates a second output voltage based on third and fourth reference voltages to provide the second output voltage to the second node. The second output voltage is maintained between the third and fourth reference voltages, and the second output voltage of the second node is provided as an internal supply voltage. The resistive device is coupled between the first and second nodes.

Abstract: Provided is a semiconductor device including a plurality of fuse circuits. Each of the fuse circuits includes: a first signal generator generating a first signal to a first node in response to a power-up signal; a pull-down transistor pulling down a second node in response to the first signal; a pull-up transistor and a fuse which are connected in series between a power supply voltage and the second node and pulling up the second node in response to the first signal when the fuse is not cut; a buffer buffering a signal output from the second node and generating a control signal; and a standby reset transistor resetting the second node in response to the control signal output from the buffer, wherein the pull-down transistor and the standby reset transistor have threshold voltages lower than a threshold voltage of the buffer. Also, each of the fuse circuits further includes an active reset transistor resetting the second node in the active mode in response to the reset control signal.

Abstract: A circuit and method for test mode entry of a semiconductor memory device are provided. In a method of entering a semiconductor memory device into a test mode, an internal clock is generated in response to an external clock when a first condition is satisfied. An address combination signal is generated based on a first address combination and the internal clock. The semiconductor memory device is entered into the test mode using the internal clock and the address combination signal.

Abstract: A bit line sense amplifier and method thereof are provided. The example bit line sense amplifier may include a sense amplifying circuit coupled between a first bit line and a second bit line. The sense amplifying circuit may be configured to amplify a voltage difference between the first bit line and the second bit line. The example bit line sense amplifier may further include a power supply voltage providing circuit configured to provide a first power supply voltage and a second power supply voltage to the sense amplifying circuit in response to first and second bit line sensing control signals. The bit line sense amplifier may further include a bit line voltage compensation circuit configured to prevent a voltage-reduction at the first bit line and the second bit line for a delay period, the delay period including at least a period of time after a pre-charging of the first and second bit lines, in response to one or more of the first and second bit line sensing control signals.

Abstract: A semiconductor memory device is provided. The device includes an on die termination circuit controlling a termination resistance value by detecting a phase change of a signal inputted through a pad. Additionally, the on die termination circuit changes the termination resistance value when an identical phase signal is inputted during n (n is positive integer) periods of a clock signal.

Abstract: Disclosed herein are a semiconductor method and device which are capable of reducing data write errors by rewriting last write data during a write recovery time (tWR). The semiconductor device comprises a memory cell array consisting of a plurality of repetitive cell units; a bit line amplifier for amplifying a voltage difference between a bit line voltage and a complementary bit line voltage of the memory cell array; switching devices activated by a column selection line signal for electrically connecting a data line and a complementary data line to the bit line and the complementary bit line, respectively; and a write driver for supplying a write data voltage to the data line and the complementary data line, wherein the column selection line signal is generated during a write recovery time.

Abstract: A reference voltage generator generates an output reference voltage having various voltage levels. The reference voltage generator includes an amplifier to amplify a difference between a feedback reference voltage and a feedback voltage to generate an amplified signal, a current driving circuit to provide a current signal in response to the amplified signal, a scaler circuit to generate feedback voltage signals and reference voltage signals in response to the current signal, and a feedback voltage selecting circuit to select one of the feedback voltage signals in response to a control signal, and to provide the selected feedback voltage signal to the operational amplifier as the feedback voltage.

Abstract: A circuit and method for test mode entry of a semiconductor memory device are provided. In a method of entering a semiconductor memory device into a test mode, an internal clock is generated in response to an external clock when a first condition is satisfied. An address combination signal is generated based on a first address combination and the internal clock. The semiconductor memory device is entered into the test mode using the internal clock and the address combination signal.

Abstract: A DLL power supply of the integrated circuit memory device supplies power to the DLL circuit, and a control signal generator controls the DLL power supply to selectively supply power to the DLL circuit during a refresh mode of the integrated circuit memory device based on a selection signal.

Abstract: Disclosed herein are a semiconductor method and device which are capable of reducing data write errors by rewriting last write data during a write recovery time (tWR). The semiconductor device comprises a memory cell array consisting of a plurality of repetitive cell units; a bit line amplifier for amplifying a voltage difference between a bit line voltage and a complementary bit line voltage of the memory cell array; switching devices activated by a column selection line signal for electrically connecting a data line and a complementary data line to the bit line and the complementary bit line, respectively; and a write driver for supplying a write data voltage to the data line and the complementary data line, wherein the column selection line signal is generated during a write recovery time.

Abstract: In a data output circuit for reducing a skewing error of a data signal, a first inversion unit receives a first data signal of an operating voltage level and inverts the received first data signal to obtain a first inverted data signal. If a first power supply voltage of an output voltage level is different from a second power supply voltage with the operating voltage level by at least a predetermined voltage level, a first voltage compensation unit compensates for the voltage level of the first inverted data signal to obtain a first driving signal. A second inversion unit receives a second data signal with the operating voltage level and inverts the received second data signal to obtain a second inverted data signal. If the levels of the first and second power supply voltages are different by at least a predetermined voltage level, a second voltage compensation unit compensates for the voltage level of the second inverted data signal to obtain a second driving signal.

Abstract: A DLL power supply of the integrated circuit memory device supplies power to the DLL circuit, and a control signal generator controls the DLL power supply to selectively supply power to the DLL circuit during a refresh mode of the integrated circuit memory device based on a selection signal.

Abstract: A data buffer circuit includes first and second driver circuits coupled to the data latch circuit and operative to respectively pull up and pull down their outputs towards respective first and second voltages responsive to first and second data signals. An output circuit includes first and second transistors connected at an output node and operative to respectively pull up and pull down the output node toward respective ones of the first and second voltages responsive to respective ones of the outputs of the first and second driver circuits. A transition compensation circuit is operative to control relative rates at the output node of the output circuit transitions toward the first and second voltages responsive to a transition rate control signal.

Abstract: In a data output circuit for reducing a skewing error of a data signal, a first inversion unit receives a first data signal of an operating voltage level and inverts the received first data signal to obtain a first inverted data signal. If a first power supply voltage of an output voltage level is different from a second power supply voltage with the operating voltage level by at least a predetermined voltage level, a first voltage compensation unit compensates for the voltage level of the first inverted data signal to obtain a first driving signal. A second inversion unit receives a second data signal with the operating voltage level and inverts the received second data signal to obtain a second inverted data signal. If the levels of the first and second power supply voltages are different by at least a predetermined voltage level, a second voltage compensation unit compensates for the voltage level of the second inverted data signal to obtain a second driving signal.

Abstract: Integrated circuit memory devices according to the present invention include a sense amplifier having a pair of differential input signal lines, a pair of differential output signal lines, and a current amplifier. The current amplifier has an input stage electrically coupled to the pair of differential input signal lines and an output stage electrically coupled to the pair of differential output signal lines. The input stage and/or the output stage are responsive to a first control signal that reduces a gain of the current amplifier when the first control signal is asserted.

Abstract: A data buffer circuit includes first and second driver circuits coupled to the data latch circuit and operative to respectively pull up and pull down their outputs towards respective first and second voltages responsive to first and second data signals. An output circuit includes first and second transistors connected at an output node and operative to respectively pull up and pull down the output node toward respective ones of the first and second voltages responsive to respective ones of the outputs of the first and second driver circuits. A transition compensation circuit is operative to control relative rates at the output node of the output circuit transitions toward the first and second voltages responsive to a transition rate control signal.

Abstract: An input circuit having one or more individual signature circuits connected in parallel between an input line and an voltage node in a semiconductor device and an individual signature circuit are provided. The individual signature circuits are isolated from an input/output port to which a high frequency signal is applied so that the input/output port of the semiconductor device can operate at high speed. The signature circuits are provided for an input/output port to which a relatively low frequency signal is applied. An individual signature circuit includes an indexer and a selector connected in series between the voltage node and the input line. The selector includes two terminals which are electrically short-circuited or snapped in response to a control signal, and the indexer includes one or more voltage reducing devices connected in series between input and output terminals of the indexer and signature fuses each of which is connected in parallel to corresponding one of the voltage reducing devices.

Abstract: Integrated circuit memory devices according to the present invention include a sense amplifier having a pair of differential input signal lines, a pair of differential output signal lines, and a current amplifier. The current amplifier has an input stage electrically coupled to the pair of differential input signal lines and an output stage electrically coupled to the pair of differential output signal lines. The input stage and/or the output stage are responsive to a first control signal that reduces a gain of the current amplifier when the first control signal is asserted.

Abstract: An integrated circuit memory device includes a memory cell array and first and second sense amplifiers positioned on respective opposite first and second sides of the memory cell array. A first bit line pair and a second bit line pair connect the memory cell array to the first and second sense amplifiers, respectively. A first bit line of the first bit line pair and a first bit line of the second bit line pair extend across the memory cell array from the first side to the second side without crossing one another. A second bit line of the second bit line pair extends across the memory cell array from the first side to the second side, crossing the first bit line of the first bit line pair and the first bit line of the second bit line pair.