Abstract: An internal power supply circuit for use in a semiconductor device includes a clamp circuit for clamping an internal voltage to a constant level. The clamped internal voltage is distributed to internal circuits of the semiconductor device through an output node. When the internal voltage rises momentarily due to noise in the internal power supply circuit due to open-circuit phenomenon, the rising internal voltage is discharged through the clamp circuit, thereby maintaining the internal voltage at a constant value. The clamp circuit includes a first transistor for discharging the output node, and a diode-connected transistor for generating a charge voltage at the gate of the first transistor. The threshold voltage of the diode-connected transistor is preferably equal to or lower than the threshold voltage of the first transistor.

Abstract: A dual-purpose transmission circuit capable of receiving two or more signals or voltages, or a signal and a voltage, using one input pad, and an input method using the circuit. The dual-purpose transmission circuit includes an internal signal line for transmitting a signal to the inside of the semiconductor device, an internal voltage line for transmitting a voltage to the inside of the semiconductor device, a first transmission portion for connecting the internal signal line to the outside of the semiconductor device in response to a control signal, in a signal input mode, and a second transmission portion for connecting the internal voltage line to the outside of the semiconductor device in response to the control signal, in a voltage input mode.

Abstract: External address signals are applied to an integrated circuit in a burn-in test mode. The external address signals control the voltage levels of adjacent main word lines in a memory array in the integrated circuit. The adjacent main word lines may thereby be configured in to be in opposing logic states. The opposing logic states may provide a potential difference between the adjacent main word lines, thereby increasing the likelihood of detecting microbridges between the adjacent main word lines formed during fabrication of the integrated circuit. The reliability of the integrated circuit may thereby be improved.

Abstract: Integrated circuit devices include preferred mode selection circuits therein which generate a signal that designates a first mode of the integrated circuit device when a potential of a first control signal is within a first range and a potential of a power supply signal (e.g., Vcc) is within a second range at the same time. The mode selection circuit also prevents changes in the potential of the first control signal from disabling the first mode when the potential of the power supply signal is not within the second range. When the integrated circuit device is a memory device, the first control signal may be a row or column address signal (Ai), for example. The mode selection circuit may comprise a level shifter which generates a downward level shifted version of the address signal. The mode selection circuit generates a signal that designates a first mode of the memory device when a potential of the address signal exceeds a first threshold (e.g.

Abstract: Multi-bank integrated circuit memory devices include first and second memory cell arrays having first and second pairs of differential bit lines electrically coupled thereto, respectively. A dual sense amplifier is also provided and this sense amplifier is electrically coupled together by a first pair of differential input/output lines. First and second isolation circuits are also provided. The first isolation circuit is electrically coupled to the first pair of differential bit lines and is responsive to a first control signal (C1). The second isolation circuit is electrically coupled to the second pair of differential bit lines and is responsive to a second control signal (C2). First and second equalization circuits are provided. The first equalization circuit is responsive to the second control signal and performs the function of equalizing a potential of the first pair of differential bit lines.

Abstract: An internal voltage conversion circuit for a DRAM wherein a voltage level of an internal power supply is regulated by an external signal applied to the DRAM pins after packaging to perform reliability tests. The internal voltage conversion circuit includes a test mode signal generator, for generating a test mode signal by combining first control signals applied externally of the semiconductor device, and a switching signal generator, for generating first and second switching signals according to second control signals applied externally of the DRAM when the test mode signal is active. First and second switching resistor portions connected in series between the internal power supply port and a ground potential are switched by the first and second switching signals, respectively, so that their resistance values are changed. The resistor portions are in a feedback path connected to one input of a comparator. The other input is connected to a reference cell.