Patents by Inventor Jong-koo Lim

Jong-koo Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11770980
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a multilayer synthetic anti-ferromagnetic (Multi SAF) structure including a first ferromagnetic layer, a second ferromagnetic layer, and a spacer layer interposed between the first ferromagnetic layer and the second ferromagnetic layer, wherein the spacer layer may include n non-magnetic layers and n?1 magnetic layers that are disposed such that each of the n non-magnetic layers and each of the n?1 magnetic layers are alternately stacked, wherein n indicates an odd number equal to or greater than 3, wherein the n?1 magnetic layers and n non-magnetic layers may be configured to effectuate an antiferromagnetic exchange coupling with at least one of the first ferromagnetic layer and the second ferromagnetic layer.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: September 26, 2023
    Assignee: SK HYNIX INC.
    Inventors: Tae Young Lee, Guk Cheon Kim, Soo Gil Kim, Min Seok Moon, Jong Koo Lim, Sung Woong Chung
  • Patent number: 11730062
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a magnetic tunnel junction (MTJ) structure including a free layer, a pinned layer, and a tunnel barrier layer, the free layer having a variable magnetization direction, the pinned layer having a fixed magnetization direction, the tunnel barrier layer being interposed between the free layer and the pinned layer; and a thermal stability enhanced layer (TSEL) including a homogeneous material having an Fe—O bond.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: August 15, 2023
    Assignees: SK hynix Inc., Kioxia Corporation
    Inventors: Tae Young Lee, Guk Cheon Kim, Soo Gil Kim, Soo Man Seo, Jong Koo Lim, Taiga Isoda
  • Publication number: 20230026414
    Abstract: According to one embodiment, a magnetoresistive memory device includes: a first ferromagnetic layer; a stoichiometric first layer; a first insulator between the first ferromagnetic layer and the first layer; a second ferromagnetic layer between the first insulator and the first layer; and a non-stoichiometric second layer between the second ferromagnetic layer and the first layer. The second layer is in contact with the second ferromagnetic layer and the first layer.
    Type: Application
    Filed: October 3, 2022
    Publication date: January 26, 2023
    Applicants: KIOXIA CORPORATION, SK HYNIX INC.
    Inventors: Taiga ISODA, Eiji KITAGAWA, Young Min Min EEH, Tadaaki OIKAWA, Kazuya SAWADA, Kenichi YOSHINO, Jong Koo LIM, Ku Youl JUNG, Guk Cheon Cheon KIM
  • Patent number: 11495740
    Abstract: According to one embodiment, a magnetoresistive memory device includes: a first ferromagnetic layer; a stoichiometric first layer; a first insulator between the first ferromagnetic layer and the first layer; a second ferromagnetic layer between the first insulator and the first layer; and a non-stoichiometric second layer between the second ferromagnetic layer and the first layer. The second layer is in contact with the second ferromagnetic layer and the first layer.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: November 8, 2022
    Assignees: KIOXIA CORPORATION, SK HYNIX INC.
    Inventors: Taiga Isoda, Eiji Kitagawa, Young Min Eeh, Tadaaki Oikawa, Kazuya Sawada, Kenichi Yoshino, Jong Koo Lim, Ku Youl Jung, Guk Cheon Kim
  • Publication number: 20210184101
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a multilayer synthetic anti-ferromagnetic (Multi SAF) structure including a first ferromagnetic layer, a second ferromagnetic layer, and a spacer layer interposed between the first ferromagnetic layer and the second ferromagnetic layer, wherein the spacer layer may include n non-magnetic layers and n?1 magnetic layers that are disposed such that each of the n non-magnetic layers and each of the n?1 magnetic layers are alternately stacked, wherein n indicates an odd number equal to or greater than 3, wherein the n?1 magnetic layers and n non-magnetic layers may be configured to effectuate an antiferromagnetic exchange coupling with at least one of the first ferromagnetic layer and the second ferromagnetic layer.
    Type: Application
    Filed: August 12, 2020
    Publication date: June 17, 2021
    Inventors: Tae Young Lee, Guk Cheon Kim, Soo Gil Kim, Min Seok Moon, Jong Koo Lim, Sung Woong Chung
  • Publication number: 20210184102
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a magnetic tunnel junction (MTJ) structure including a free layer, a pinned layer, and a tunnel barrier layer, the free layer having a variable magnetization direction, the pinned layer having a fixed magnetization direction, the tunnel barrier layer being interposed between the free layer and the pinned layer; and a thermal stability enhanced layer (TSEL) including a homogeneous material having an Fe—O bond.
    Type: Application
    Filed: September 25, 2020
    Publication date: June 17, 2021
    Inventors: Tae Young LEE, Guk Cheon KIM, Soo Gil KIM, Soo Man SEO, Jong Koo LIM, Taiga ISODA
  • Patent number: 10978637
    Abstract: A method for fabricating an electronic device including a semiconductor memory may include forming a buffer layer over a substrate, the buffer layer operable to aide in crystal growth of an under layer; forming the under layer over the buffer layer, the under layer operable to aide in crystal growth of a free layer; and forming a Magnetic Tunnel Junction (MTJ) structure including the free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer over the under layer.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: April 13, 2021
    Assignee: SK hynix Inc.
    Inventors: Ku-Youl Jung, Guk-Cheon Kim, Jong-Koo Lim, Yang-Kon Kim, Jae-Hyoung Lee
  • Publication number: 20210074911
    Abstract: According to one embodiment, a magnetoresistive memory device includes: a first ferromagnetic layer; a stoichiometric first layer; a first insulator between the first ferromagnetic layer and the first layer; a second ferromagnetic layer between the first insulator and the first layer; and a non-stoichiometric second layer between the second ferromagnetic layer and the first layer. The second layer is in contact with the second ferromagnetic layer and the first layer.
    Type: Application
    Filed: March 10, 2020
    Publication date: March 11, 2021
    Applicants: KIOXIA CORPORATION, SK HYNIX INC.
    Inventors: Taiga ISODA, Eiji KITAGAWA, Young Min EEH, Tadaaki OIKAWA, Kazuya SAWADA, Kenichi YOSHINO, Jong Koo LIM, Ku Youl JUNG, Guk Cheon KIM
  • Patent number: 10923168
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a variable resistance element including a Magnetic Tunnel Junction (MTJ) structure including a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer; a first protective layer disposed on a lower sidewall of the variable resistance element; and a second protective layer disposed on an upper sidewall of the variable resistance element, wherein any one layer of the first protective layer and the second protective layer may apply a compressive stress to the variable resistance element, and the other layer applies a tensile stress to the variable resistance element.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: February 16, 2021
    Assignee: SK hynix Inc.
    Inventors: Jong-Koo Lim, Ku-Youl Jung, Jae-Hyoung Lee, Jeong-Myeong Kim, Tae-Young Lee
  • Patent number: 10777742
    Abstract: Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: September 15, 2020
    Assignee: SK hynix Inc.
    Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim
  • Patent number: 10685692
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer including a CoFeBAl alloy and having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein the CoFeBAl alloy may have an Al content less than 10 at %.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: June 16, 2020
    Assignee: SK hynix Inc.
    Inventors: Jong-Koo Lim, Yang-Kon Kim, Ku-Youl Jung, Guk-Cheon Kim, Jeong-Myeong Kim
  • Publication number: 20200185017
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a variable resistance element including a Magnetic Tunnel Junction (MTJ) structure including a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer; a first protective layer disposed on a lower sidewall of the variable resistance element; and a second protective layer disposed on an upper sidewall of the variable resistance element, wherein any one layer of the first protective layer and the second protective layer may apply a compressive stress to the variable resistance element, and the other layer applies a tensile stress to the variable resistance element.
    Type: Application
    Filed: February 18, 2020
    Publication date: June 11, 2020
    Inventors: Jong-Koo Lim, Ku-Youl Jung, Jae-Hyoung Lee, Jeong-Myeong Kim, Tae-Young Lee
  • Publication number: 20200098984
    Abstract: Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.
    Type: Application
    Filed: November 25, 2019
    Publication date: March 26, 2020
    Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim
  • Patent number: 10586917
    Abstract: Provided is a method for fabricating an electronic device including a variable resistance element which includes a free layer formed over a substrate and having a changeable magnetization direction, a pinned layer having a pinned magnetization direction, a tunnel barrier layer interposed between the free layer and the pinned layer, and a magnetic correction layer suitable for reducing the influence of a stray field generated by the pinned layer. The method may include: cooling the substrate; and forming the magnetic correction layer over the cooled substrate.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: March 10, 2020
    Assignees: SK hynix Inc., TOSHIBA MEMORY CORPORATION
    Inventors: Jong-Koo Lim, Won-Joon Choi, Guk-Cheon Kim, Yang-Kon Kim, Ku-Youl Jung, Toshihiko Nagase, Youngmin Eeh, Daisuke Watanabe, Kazuya Sawada, Makoto Nagamine
  • Patent number: 10566041
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a variable resistance element including a Magnetic Tunnel Junction (MTJ) structure including a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer; a first protective layer disposed on a lower sidewall of the variable resistance element; and a second protective layer disposed on an upper sidewall of the variable resistance element, wherein any one layer of the first protective layer and the second protective layer may apply a compressive stress to the variable resistance element, and the other layer applies a tensile stress to the variable resistance element.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: February 18, 2020
    Assignee: SK hynix Inc.
    Inventors: Jong-Koo Lim, Ku-Youl Jung, Jae-Hyoung Lee, Jeong-Myeong Kim, Tae-Young Lee
  • Patent number: 10490741
    Abstract: Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: November 26, 2019
    Assignee: SK hynix Inc.
    Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim
  • Patent number: 10395708
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a fixed magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein the free layer may include: a first sublayer having a damping constant of 0.1 or less; a second sublayer having a perpendicular magnetic anisotropy energy density ranging from 1.0×104 to 1.0×108 erg/cm3; and an insertion layer interposed between the first sublayer and the second sublayer.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: August 27, 2019
    Assignee: SK hynix Inc.
    Inventors: Ku-Youl Jung, Jong-Koo Lim, Yang-Kon Kim, Jae-Hyoung Lee
  • Patent number: 10305030
    Abstract: Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: May 28, 2019
    Assignee: SK hynix Inc.
    Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim, Jeong-Myeong Kim
  • Patent number: 10305028
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include an MTJ (Magnetic Tunnel Junction) structure including a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer; an under layer disposed under the MTJ structure; and a perpendicular magnetic anisotropy increasing layer disposed below the under layer and including a material having a different crystal structure from the under layer.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: May 28, 2019
    Assignee: SK hynix Inc.
    Inventors: Yang-Kon Kim, Ku-Youl Jung, Jong-Koo Lim, Jae-Hyoung Lee
  • Publication number: 20190109280
    Abstract: Provided is a method for fabricating an electronic device including a variable resistance element which includes a free layer formed over a substrate and having a changeable magnetization direction, a pinned layer having a pinned magnetization direction, a tunnel barrier layer interposed between the free layer and the pinned layer, and a magnetic correction layer suitable for reducing the influence of a stray field generated by the pinned layer. The method may include: cooling the substrate; and forming the magnetic correction layer over the cooled substrate.
    Type: Application
    Filed: November 28, 2018
    Publication date: April 11, 2019
    Inventors: Jong-Koo LIM, Won-Joon CHOI, Guk-Cheon KIM, Yang-Kon KIM, Ku-Youl JUNG, Toshihiko NAGASE, Youngmin EEH, Daisuke WATANABE, Kazuya SAWADA, Makoto NAGAMINE