Patents by Inventor Jong-koo Lim
Jong-koo Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190074042Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a variable resistance element including a Magnetic Tunnel Junction (MTJ) structure including a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer; a first protective layer disposed on a lower sidewall of the variable resistance element; and a second protective layer disposed on an upper sidewall of the variable resistance element, wherein any one layer of the first protective layer and the second protective layer may apply a compressive stress to the variable resistance element, and the other layer applies a tensile stress to the variable resistance element.Type: ApplicationFiled: August 6, 2018Publication date: March 7, 2019Inventors: Jong-Koo Lim, Ku-Youl Jung, Jae-Hyoung Lee, Jeong-Myeong Kim, Tae-Young Lee
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Publication number: 20190074041Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a fixed magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein the free layer may include: a first sublayer having a damping constant of 0.1 or less; a second sublayer having a perpendicular magnetic anisotropy energy density ranging from 1.0×104 to 1.0×108 erg/cm3; and an insertion layer interposed between the first sublayer and the second sublayer.Type: ApplicationFiled: August 6, 2018Publication date: March 7, 2019Inventors: Ku-Youl Jung, Jong-Koo Lim, Yang-Kon Kim, Jae-Hyoung Lee
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Patent number: 10170691Abstract: Provided is a method for fabricating an electronic device including a variable resistance element which includes a free layer formed over a substrate and having a changeable magnetization direction, a pinned layer having a pinned magnetization direction, a tunnel barrier layer interposed between the free layer and the pinned layer, and a magnetic correction layer suitable for reducing the influence of a stray field generated by the pinned layer. The method may include: cooling the substrate; and forming the magnetic correction layer over the cooled substrate.Type: GrantFiled: June 20, 2016Date of Patent: January 1, 2019Assignees: SK Hynix Inc., TOSHIBA MEMORY CORPORATIONInventors: Jong-Koo Lim, Won-Joon Choi, Guk-Cheon Kim, Yang-Kon Kim, Ku-Youl Jung, Toshihiko Nagase, Youngmin Eeh, Daisuke Watanabe, Kazuya Sawada, Makoto Nagamine
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Patent number: 10153423Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; a tunnel barrier layer interposed between the free layer and the pinned layer; and an under layer which is in contact with the free layer and includes a rare earth metal nitride.Type: GrantFiled: December 15, 2017Date of Patent: December 11, 2018Assignees: SK Hynix Inc., Toshiba Memory CorporationInventors: Yang-Kon Kim, Guk-Cheon Kim, Jae-Hyoung Lee, Jong-Koo Lim, Ku-Youl Jung, Toshihiko Nagase, Youngmin Eeh
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Patent number: 10134458Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: an under layer including first and second metal layers and a barrier layer having a dual phase structure of different crystal structures and interposed between the first and second metal layers; a first magnetic layer positioned over the under layer and having a variable magnetization direction; a tunnel barrier layer positioned over the first magnetic layer; and a second magnetic layer positioned over the tunnel barrier layer and having a pinned magnetization direction, and the under layer may further include a barrier layer having a dual phase structure between the first and second metal layers.Type: GrantFiled: January 8, 2018Date of Patent: November 20, 2018Assignee: SK hynix Inc.Inventors: Yang-Kon Kim, Bo-Mi Lee, Won-Joon Choi, Guk-Cheon Kim, Jong-Koo Lim
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Publication number: 20180323368Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include an MTJ (Magnetic Tunnel Junction) structure including a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer; an under layer disposed under the MTJ structure; and a perpendicular magnetic anisotropy increasing layer disposed below the under layer and including a material having a different crystal structure from the under layer.Type: ApplicationFiled: March 2, 2018Publication date: November 8, 2018Inventors: Yang-Kon Kim, Ku-Youl Jung, Jong-Koo Lim, Jae-Hyoung Lee
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Publication number: 20180277745Abstract: According to one embodiment, a magnetic memory device includes a magnetoresistive element, the magnetoresistive element including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer. The first magnetic layer includes first and second sub-magnetic layers each containing at least iron (Fe) and boron (B), and a concentration of boron (B) contained in the first sub-magnetic layer is different from a concentration of boron (B) contained in the second sub-magnetic layer.Type: ApplicationFiled: September 12, 2017Publication date: September 27, 2018Applicants: TOSHIBA MEMORY CORPORATION, SK HYNIX INC.Inventors: Tadaaki OIKAWA, Toshihiko NAGASE, Youngmin EEH, Daisuke WATANABE, Kazuya SAWADA, Kenichi YOSHINO, Hiroyuki OHTORI, Yang Kon KIM, Ku Youl JUNG, Jong Koo LIM, Jae Hyoung LEE, Soo Man SEO, Sung Woong CHUNG, Tae Young LEE
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Patent number: 10062424Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory, and the semiconductor memory may include: an under layer including a plurality of material layers having a different crystal structures; a first magnetic layer formed over the under layer and having a variable magnetization direction; a tunnel barrier layer formed over the first magnetic layer; and a second magnetic layer formed over the tunnel barrier layer and having a pinned magnetization direction.Type: GrantFiled: July 17, 2017Date of Patent: August 28, 2018Assignee: SK hynix Inc.Inventors: Yang-Kon Kim, Guk-Cheon Kim, Jeong-Myeong Kim, Jong-Koo Lim, Ku-Youl Jung, Won-Joon Choi
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Publication number: 20180240973Abstract: A method for fabricating an electronic device including a semiconductor memory may include forming a buffer layer over a substrate, the buffer layer operable to aide in crystal growth of an under layer; forming the under layer over the buffer layer, the under layer operable to aide in crystal growth of a free layer; and forming a Magnetic Tunnel Junction (MTJ) structure including the free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer over the under layer.Type: ApplicationFiled: February 2, 2018Publication date: August 23, 2018Inventors: Ku-Youl Jung, Guk-Cheon Kim, Jong-Koo Lim, Yang-Kon Kim, Jae-Hyoung Lee
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Publication number: 20180233187Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer including a CoFeBAl alloy and having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein the CoFeBAl alloy may have an Al content less than 10 at %.Type: ApplicationFiled: January 22, 2018Publication date: August 16, 2018Inventors: Jong-Koo Lim, Yang-Kon Kim, Ku-Youl Jung, Guk-Cheon Kim, Jeong-Myeong Kim
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Patent number: 10042559Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory for storing data, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; a tunnel barrier layer interposed between the free layer and the pinned layer; and an interface enhancement layer interposed between the tunnel barrier layer and the pinned layer, wherein the interface enhancement layer may include an Fe-rich first layer; a Co-rich second layer formed over the first layer; and a metal layer formed over the second layer.Type: GrantFiled: January 30, 2017Date of Patent: August 7, 2018Assignee: SK hynix Inc.Inventors: Yang-Kon Kim, Guk-Cheon Kim, Ku-Youl Jung, Jong-Koo Lim, Won-Joon Choi
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Publication number: 20180211994Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory may include an MTJ (Magnetic Tunnel Junction) structure including a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer; and an under layer formed under the MTJ structure, wherein the under layer may include metals and oxides of the metals.Type: ApplicationFiled: November 2, 2017Publication date: July 26, 2018Inventors: Guk-Cheon Kim, Ku-Youl Jung, Yang-Kon Kim, Jae-Hyoung Lee, Jong-Koo Lim
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Publication number: 20180198060Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; a tunnel barrier layer interposed between the free layer and the pinned layer; and an under layer which is in contact with the free layer and includes a rare earth metal nitride.Type: ApplicationFiled: December 15, 2017Publication date: July 12, 2018Inventors: Yang-Kon KIM, Guk-Cheon KIM, Jae-Hyoung LEE, Jong-Koo LIM, Ku-Youl JUNG, Toshihiko NAGASE, Youngmin EEH
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Patent number: 10002903Abstract: Implementations of the disclosed technology provide an electronic device including a semiconductor memory, wherein the semiconductor memory includes: a magnetic tunnel junction (MTJ) structure including a free layer having a changeable magnetization direction, a pinned layer having a pinned magnetization direction, and a tunnel barrier layer sandwiched between the free layer and the pinned layer; and an under layer located under the MTJ structure, wherein the under layer includes a first under layer including a silicon-based alloy, and a second under layer located on the first under layer and including a metal.Type: GrantFiled: March 18, 2016Date of Patent: June 19, 2018Assignee: SK hynix Inc.Inventors: Jong-Koo Lim, Guk-Cheon Kim, Yang-Kon Kim, Ku-Youl Jung, Won-Joon Choi
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Publication number: 20180130512Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: an under layer including first and second metal layers and a barrier layer having a dual phase structure of different crystal structures and interposed between the first and second metal layers; a first magnetic layer positioned over the under layer and having a variable magnetization direction; a tunnel barrier layer positioned over the first magnetic layer; and a second magnetic layer positioned over the tunnel barrier layer and having a pinned magnetization direction, and the under layer may further include a barrier layer having a dual phase structure between the first and second metal layers.Type: ApplicationFiled: January 8, 2018Publication date: May 10, 2018Inventors: Yang-Kon Kim, Bo-Mi Lee, Won-Joon Choi, Guk-Cheon Kim, Jong-Koo Lim
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Publication number: 20180130945Abstract: Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.Type: ApplicationFiled: January 8, 2018Publication date: May 10, 2018Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim, Jeong-Myeong Kim
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Patent number: 9865799Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a pinned layer having a pinned magnetization direction; a free layer having a changeable magnetization direction; a tunnel barrier layer interposed between the pinned layer and the free layer, and including a metal oxide; and a carbon-based compound patch positioned at one or more of between the pinned layer and the tunnel barrier layer, between the free layer and the tunnel barrier layer, and in the tunnel barrier layer.Type: GrantFiled: October 20, 2016Date of Patent: January 9, 2018Assignee: SK hynix Inc.Inventors: Jeong-Myeong Kim, June-Seo Kim, Jong-Koo Lim, Jung-Hwan Moon, Sung-Joon Yoon
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Patent number: 9865319Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: an under layer including first and second metal layers and a barrier layer having a dual phase structure of different crystal structures and interposed between the first and second metal layers; a first magnetic layer positioned over the under layer and having a variable magnetization direction; a tunnel barrier layer positioned over the first magnetic layer; and a second magnetic layer positioned over the tunnel barrier layer and having a pinned magnetization direction, and the under layer may further include a barrier layer having a dual phase structure between the first and second metal layers.Type: GrantFiled: September 6, 2015Date of Patent: January 9, 2018Assignee: SK hynix Inc.Inventors: Yang-Kon Kim, Bo-Mi Lee, Won-Joon Choi, Guk-Cheon Kim, Jong-Koo Lim
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Patent number: 9865806Abstract: Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.Type: GrantFiled: November 17, 2016Date of Patent: January 9, 2018Assignee: SK hynix Inc.Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim, Jeong-Myeong Kim
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Patent number: 9847474Abstract: An electronic device may include a semiconductor memory. The semiconductor memory may include a variable resistance element including a ferromagnetic layer including a hydrogen group; an oxide spacer formed on sidewalls of the variable resistance element; and a nitride spacer formed on the oxide spacer.Type: GrantFiled: February 19, 2016Date of Patent: December 19, 2017Assignee: SK hynix Inc.Inventors: Jeong-Myeong Kim, Yang-Kon Kim, Jong-Koo Lim