Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory for storing data, and the semiconductor memory may include a magnetic tunnel junction (MTJ) structure comprising a free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer; and an under layer located under the MTJ structure, wherein the under layer may include: a first under layer including a silicon-based alloy; a second under layer including a metal; and a blocking layer interposed between the first under layer and the second under layer and including an amorphous material.

Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory for storing data, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; a tunnel barrier layer interposed between the free layer and the pinned layer; and an interface enhancement layer interposed between the tunnel barrier layer and the pinned layer, wherein the interface enhancement layer may include an Fe-rich first layer; a Co-rich second layer formed over the first layer; and a metal layer formed over the second layer.

Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory, and the semiconductor memory may include: an under layer including a plurality of material layers having a different crystal structures; a first magnetic layer formed over the under layer and having a variable magnetization direction; a tunnel barrier layer formed over the first magnetic layer; and a second magnetic layer formed over the tunnel barrier layer and having a pinned magnetization direction.

Abstract: According to one embodiment, a magnetoresistive memory device includes an electrode, a first layer which is provided on the electrode and includes an amorphous portion in at least a part of an electrode side, and a magnetoresisive element provided on the first layer.

Abstract: Provided are electronic device including a variable resistance element and a method for fabricating an electronic device including a variable resistance element. The electronic device including a variable resistance element includes a free layer formed over a substrate and having a changeable magnetization direction, a pinned layer having a pinned magnetization direction, a tunnel barrier layer interposed between the free layer and the pinned layer, and a magnetic correction layer suitable for reducing the influence of a stray field generated by the pinned layer. The method may include cooling the substrate, before forming the magnetic correction layer such that the magnetic correction layer is formed over the cooled substrate.

Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory, and the semiconductor memory may include: an under layer including a plurality of material layers having a different crystal structures; a first magnetic layer formed over the under layer and having a variable magnetization direction; a tunnel barrier layer formed over the first magnetic layer; and a second magnetic layer formed over the tunnel barrier layer and having a pinned magnetization direction.

Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a pinned layer having a pinned magnetization direction; a free layer having a changeable magnetization direction; a tunnel barrier layer interposed between the pinned layer and the free layer, and including a metal oxide; and a carbon-based compound patch positioned at one or more of between the pinned layer and the tunnel barrier layer, between the free layer and the tunnel barrier layer, and in the tunnel barrier layer.

Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory, and the semiconductor memory may include: an under layer including a plurality of material layers having a different crystal structures; a first magnetic layer formed over the under layer and having a variable magnetization direction; a tunnel barrier layer formed over the first magnetic layer; and a second magnetic layer formed over the tunnel barrier layer and having a pinned magnetization direction.

Abstract: Implementations of the disclosed technology provide an electronic device including a semiconductor memory, wherein the semiconductor memory includes: a magnetic tunnel junction (MTJ) structure including a free layer having a changeable magnetization direction, a pinned layer having a pinned magnetization direction, and a tunnel barrier layer sandwiched between the free layer and the pinned layer; and an under layer located under the MTJ structure, wherein the under layer includes a first under layer including a silicon-based alloy, and a second under layer located on the first under layer and including a metal.

Abstract: Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.

Abstract: Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.

Abstract: An electronic device may include a semiconductor memory. The semiconductor memory may include a variable resistance element including a ferromagnetic layer including a hydrogen group; an oxide spacer formed on sidewalls of the variable resistance element; and a nitride spacer formed on the oxide spacer.

Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: an under layer including first and second metal layers and a barrier layer having a dual phase structure of different crystal structures and interposed between the first and second metal layers; a first magnetic layer positioned over the under layer and having a variable magnetization direction; a tunnel barrier layer positioned over the first magnetic layer; and a second magnetic layer positioned over the tunnel barrier layer and having a pinned magnetization direction, and the under layer may further include a barrier layer having a dual phase structure between the first and second metal layers.

Abstract: A bipolar plate and a direct liquid feed fuel cell stack are provided. The bipolar plate includes a manifold that is coupled with the fuel/oxidant path holes and a plurality of flow channels that are coupled with the manifold. The flow channels are divided into a plurality of groups, where the flow channel of each group forms a serpentine flow path and a length of each flow channel is substantially the same.

Abstract: A bipolar plate for fuel cells includes a plurality of flow paths in which fuel flows. The flow paths include a first flow path formed by a plurality of flow channels and a second flow path formed by a plurality of islands. A direct liquid fuel cell stack comprises the bipolar plate.

Abstract: A bipolar plate and a direct liquid feed fuel cell stack are provided. The bipolar plate includes a manifold that is coupled with the fuel/oxidant path holes and a plurality of flow channels that are coupled with the manifold. The flow channels are divided into a plurality of groups, where the flow channel of each group forms a serpentine flow path and a length of each flow channel is substantially the same.

Abstract: A bipolar plate for fuel cells includes a plurality of flow paths in which fuel flows. The flow paths include a first flow path formed by a plurality of flow channels and a second flow path formed by a plurality of islands. A direct liquid fuel cell stack comprises the bipolar plate.