Patents by Inventor Jong Moo Choi

Jong Moo Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150006794
    Abstract: The present invention relates to an apparatus and method for controlling multi-way NAND flashes using input-output pins. The apparatus for controlling multi-way NAND flashes includes: a NAND flash monitor for confirming each state of a plurality of NAND flashes by using a read status command which checks whether an inner operation of the NAND flash is performed normally; and a scheduler for determining the order in which each of the NAND flashes occupies an input-output bus.
    Type: Application
    Filed: December 10, 2012
    Publication date: January 1, 2015
    Applicant: Industry-University Cooperation Foundation Hanyang University
    Inventors: Soo Yong Kang, You Jip Won, Jae Hyuk Cha, Sung Roh Yoon, Myung Hyun Rhee, Jong Moo Choi
  • Publication number: 20140380092
    Abstract: Provided is a control device for managing a plurality of memory channels driven through multichannel interleaving. The apparatus includes a stripe configuring unit for configuring a stripe according to a physical number of pages included in the plurality of memory channels, and a parity generating unit for generating parity data on the configured stripe.
    Type: Application
    Filed: February 8, 2013
    Publication date: December 25, 2014
    Inventors: Jae Ho Kim, Jong Min Lee, Jong Moo Choi, Dong Hee Lee, Sam Hyuk Noh
  • Publication number: 20140372681
    Abstract: The present invention relates to an apparatus and method for indicating flash memory life. While data is being stored in a flash memory, the number of writes in a plurality of blocks of the flash memory increases. The amount of flash memory life is calculated on the basis of the number of write times in the plurality of blocks. The calculated amount of life can be transmitted to a host. In addition, when the calculated amount of life is greater than a threshold value, a signal providing notice that the life of the flash memory has reached a dangerous level can be output.
    Type: Application
    Filed: December 10, 2012
    Publication date: December 18, 2014
    Applicant: Industry-University Cooperation Foundation Hanyang University
    Inventors: Jae Hyuk Cha, Soo Yong Kang, You Jip Won, Tae Hwa Lee, Ho Young Jung, Sung Roh Yoon, Jong Moo Choi
  • Publication number: 20140342519
    Abstract: A three-dimensional (3-D) non-volatile memory device includes channel structures each including channel layers stacked over a substrate and extending in a first direction, wherein the channel layers include well regions, respectively, vertical gates located and spaced from each other between the channel structures, and a well pick-up line contacting on the well regions of the channel layers and extending in a second direction crossing the channel structures.
    Type: Application
    Filed: July 31, 2014
    Publication date: November 20, 2014
    Inventors: Yoo Hyun NOH, Jong Moo CHOI, Young Soo AHN
  • Publication number: 20140337596
    Abstract: The present invention relates to a grouping method and device for enhancing redundancy removing performance for a storage unit such as a hard disk, a solid state disk (SSD), etc. The grouping method for enhancing performance of a redundancy removing technology may include: extracting samples from data that is stored in a buffer of a memory and is standing by to be processed; performing remaining calculations on the extracted samples; and grouping samples by connecting them to a bucket corresponding to a resultant value of the remaining calculations.
    Type: Application
    Filed: December 10, 2012
    Publication date: November 13, 2014
    Inventors: Soo Yong Kang, You Jip Won, Jae Hyuk Cha, Jong Moo Choi, Sung Roh Yoon, Jong Hwa Kim, Ik Joon Son, Sang Yup Lee
  • Patent number: 8887139
    Abstract: A virtual system comprises hardware, a virtualization layer virtualizing the hardware, a virtual machine monitor, a user domain operating using the virtualized hardware, and a root domain operating using the virtualized hardware and managing the user domain. The virtual machine monitor analyzes an operation performed by the user domain in real time and stores resulting analysis information in the root domain.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mi-Kyoung Park, Jong Moo Choi, Jong Hwa Kim, Hee Kwon Park
  • Publication number: 20140295641
    Abstract: A semiconductor memory device includes a semiconductor substrate in which an active region and an isolation region are defined, a tunnel insulating layer and a floating gate formed on the semiconductor substrate in the active region, a trench formed in the semiconductor substrate in the isolation region, a dielectric layer formed along a top surface and a portion of a side surface of the floating gate, wherein the dielectric layer extends higher than a surface of the semiconductor substrate in the isolation region and defines an air gap in the trench, and a control gate formed on the dielectric layer, wherein the dielectric layer includes the first nitride layer, a first oxide layer, a second nitride layer and a second oxide layer.
    Type: Application
    Filed: June 18, 2014
    Publication date: October 2, 2014
    Inventors: Jung Il CHO, Jong Moo CHOI, Eun Joo JUNG
  • Publication number: 20140229767
    Abstract: The present invention relates to a storage device that uses a flash memory that performs power loss recovery, and to a method of power loss recovery by using the storage device using the flash memory. The storage device stores change information on metadata in physical pages in which one or more logical pages are compressed and stored. The change information on the metadata is information representing how the metadata is changed in association with data in the one or more logical pages. The storage device may synchronize the metadata in the flash memory and recover the metadata by applying the change information on the metadata to the synchronized metadata when a power supply is disrupted.
    Type: Application
    Filed: August 31, 2012
    Publication date: August 14, 2014
    Applicant: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY
    Inventors: Soo Yong Kang, You Jip Won, Jae Hyuk Cha, Dong Wook Kim, Sung Roh Yoon, Jong Moo Choi
  • Publication number: 20140223089
    Abstract: The present invention relates to a method and device for storing data in a flash memory using address mapping for supporting various block sizes. A storage device determines the size of a block that a host system uses on the basis of the size of data that the host system requests and uses the determined block size as a mapping unit. Additionally, the storage device divides a logical address space into at least one area, and maps an address using the minimum units of different mappings in each divided area.
    Type: Application
    Filed: August 31, 2012
    Publication date: August 7, 2014
    Applicant: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY
    Inventors: Soo Yong Kang, You Jip Won, Jae Hyuk Cha, Sung Min Park, Sung Roh Yoon, Jong Moo Choi
  • Publication number: 20140151779
    Abstract: A semiconductor memory device includes a semiconductor substrate in which an active region and an isolation region are defined, a tunnel insulating layer and a floating gate formed on the semiconductor substrate in the active region, a trench formed in the semiconductor substrate in the isolation region, a dielectric layer formed along a top surface and a portion of a side surface of the floating gate, wherein the dielectric layer extends higher than a surface of the semiconductor substrate in the isolation region and defines an air gap in the trench, and a control gate formed on the dielectric layer, wherein the dielectric layer includes the first nitride layer, a first oxide layer, a second nitride layer and a second oxide layer.
    Type: Application
    Filed: February 28, 2013
    Publication date: June 5, 2014
    Applicant: SK HYNIX INC.
    Inventors: Jung Il CHO, Jong Moo CHOI, Eun Joo JUNG
  • Patent number: 8687425
    Abstract: A nonvolatile memory device includes a plurality of channel structures formed over a substrate and including a plurality of interlayer dielectric layers alternately stacked with a plurality of channel layers; first and second vertical gates alternately disposed between the channel structures along one direction crossing with the channel structure and adjoining the plurality of channel layers with a memory layer interposed therebetween; and a pair of first and second word lines disposed over or under the channel structures and extending along the one direction in such a way as to overlap with the first and second vertical gates. The first word line is connected with the first vertical gates and the second word line is connected with the second vertical gates.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: April 1, 2014
    Assignee: SK Hynix Inc.
    Inventors: Young-Soo Ahn, Jong-Moo Choi, Yoo-Hyun Noh
  • Publication number: 20130170303
    Abstract: A nonvolatile memory device includes a plurality of channel structures formed over a substrate and including a plurality of interlayer dielectric layers alternately stacked with a plurality of channel layers; first and second vertical gates alternately disposed between the channel structures along one direction crossing with the channel structure and adjoining the plurality of channel layers with a memory layer interposed therebetween; and a pair of first and second word lines disposed over or under the channel structures and extending along the one direction in such a way as to overlap with the first and second vertical gates. The first word line is connected with the first vertical gates and the second word line is connected with the second vertical gates.
    Type: Application
    Filed: September 11, 2012
    Publication date: July 4, 2013
    Inventors: Young-Soo AHN, Jong-Moo Choi, Yoo-Hyun Noh
  • Publication number: 20130153979
    Abstract: A three-dimensional (3-D) non-volatile memory device includes channel structures each including channel layers stacked over a substrate and extending in a first direction, wherein the channel layers include well regions, respectively, vertical gates located and spaced from each other between the channel structures, and a well pick-up line contacting on the well regions of the channel layers and extending in a second direction crossing the channel structures.
    Type: Application
    Filed: September 6, 2012
    Publication date: June 20, 2013
    Inventors: Yoo Hyun NOH, Jong Moo Choi, Young Soo Ahn
  • Patent number: 8326020
    Abstract: Provided is a structural light based three-dimensional depth imaging method and system using signal separation coding and error correction thereof capable of detecting, removing and correcting corresponding errors between a projection apparatus and an image photographing apparatus caused by phenomena such as reflection on an object surface, blurring by a focus, and so on, using geometrical constraints between the projection apparatus and the image photographing apparatus. Here, the projection apparatus projects light, and the image photographing apparatus obtains the light. The depth imaging method includes projecting light from a projection apparatus, obtaining the light using an image photographing apparatus, and measuring a distance or a three-dimensional depth image. Therefore, it is possible to provide a structural light based three-dimensional depth imaging method and system using geometrical conditions capable of precisely obtaining three-dimensional depth information of target environment.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: December 4, 2012
    Inventors: Suk-han Lee, Jong-moo Choi, Dae-sik Kim, Seung-sub Oh
  • Publication number: 20110197018
    Abstract: Provided is a computing system and method that utilizes a non-volatile random access memory (NVRAM). A system including the NVRAM as a part of a memory or a whole memory may execute a program in the NVRAM, and, when the system is re-operated after being shut down, may restore a state and data of the program being executed in the NVRAM to an original state and thus, may provide a permanent computing environment.
    Type: Application
    Filed: October 6, 2009
    Publication date: August 11, 2011
    Inventors: Sam Hyuk Noh, Hyojin Kim, Eunsam Kim, Jong Moo Choi, Dong Hee Lee, Young-Je Moon, In Hwan Doh, Jung-Soo Park
  • Publication number: 20110113180
    Abstract: A virtual system comprises hardware, a virtualization layer virtualizing the hardware, a virtual machine monitor, a user domain operating using the virtualized hardware, and a root domain operating using the virtualized hardware and managing the user domain. The virtual machine monitor analyzes an operation performed by the user domain in real time and stores resulting analysis information in the root domain.
    Type: Application
    Filed: October 26, 2010
    Publication date: May 12, 2011
    Applicants: SAMSUNG ELECTRONICS CO., LTD., Industry-Academic Cooperation Foundation, Dankook Univ
    Inventors: Mi-Kyoung PARK, Jong Moo CHOI, Jong Hwa KIM, Hee Kwon PARK
  • Patent number: 7916932
    Abstract: A 3D depth imaging method and system are disclosed. The 3D depth imaging method involves radiating light at a measurement target object using a projection means and imaging the light using an image receiving means, and includes the steps of assigning a unique transmitting side address to a signal corresponding to each pixel of the projection means to encode the signal; projecting multiple light patterns at the projection means to transmit the signal; receiving the encoded signal at the image receiving means; separating the received signal to restore the address; and determining a pixel position of the object using the transmitting side address and the restored address. With the 3D depth imaging method and system, it is possible to exactly separate signals received by the image receiving means even when the signals are overlap and the geometrical structure of the object varies, and it is also possible to obtain a depth image that is robust against ambient environmental noise.
    Type: Grant
    Filed: February 15, 2006
    Date of Patent: March 29, 2011
    Assignee: IN-G Co., Ltd.
    Inventors: Suk-Han Lee, Jong-Moo Choi, Dae-Sik Kim, Seung-Sub Oh
  • Patent number: RE44052
    Abstract: A flash memory management method is provided. According to the method, when a request to write the predetermined data to a page to which data has been written is made, the predetermined data is written to a log block corresponding to a data block containing the page. When a request to write the predetermined data to the page again is received, the predetermined data is written to an empty free page in the log block. Even if the same page is requested to be continuously written to, the management method allows this to be processed in one log block, thereby improving the effectiveness in the use of flash memory resources.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: March 5, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bum-Soo Kim, Gui-Yong Lee, Jong-Min Kim, Ji-hyun In, Jesung Kim, Sam-hyuk Noh, Sang-Iyul Min, Dong-hee Lee, Jae-yong Jeong, Yoo-kun Cho, Jong-moo Choi
  • Patent number: RE45222
    Abstract: A flash memory management method is provided. According to the method, when a request to write the predetermined data to a page to which data has been written is made, the predetermined data is written to a log block corresponding to a data block containing the page. When a request to write the predetermined data to the page again is received, the predetermined data is written to an empty free page in the log block. Even if the same page is requested to be continuously written to, the management method allows this to be processed in one log block, thereby improving the effectiveness in the use of flash memory resources.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: October 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bum-soo Kim, Gui-young Lee, Jong-Min Kim, Ji-hyun In, Je-sung Kim, Sam-hyuk Noh, Sang-Iyul Min, Dong-hee Lee, Jae-yong Jeong, Yoo-kun Cho, Jong-moo Choi
  • Patent number: RE45577
    Abstract: A flash memory management method is provided. According to the method, when a request to write the predetermined data to a page to which data has been written is made, the predetermined data is written to a log block corresponding to a data block containing the page. When a request to write the predetermined data to the page again is received, the predetermined data is written to an empty free page in the log block. Even if the same page is requested to be continuously written to, the management method allows this to be processed in one log block, thereby improving the effectiveness in the use of flash memory resources.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: June 23, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bum-soo Kim, Gui-Yong Lee, Jong-Min Kim, Ji-hyun In, Je-sung Kim, Sam-hyuk Noh, Sang-lyul Min, Dong-hee Lee, Jae-yong Jeong, Yoo-kun Cho, Jong-moo Choi