Abstract: A method of manufacturing transistor may include forming an active layer on a base substrate, forming a sacrificial layer on the active layer, doping a first dopant ion in the active layer through a first ion implantation process, removing the sacrificial layer, forming a gate insulating layer; and forming a gate electrode on the gate insulating layer.

Abstract: A system includes a TRS system for providing a transcription service to a user of the TRS system during a phone call with a peer and a communications device of the user which includes a phone call unit associated with the phone number and a TRS call unit associated with the virtual number. The TRS system includes a database which stores a phone number and a virtual number of the user, wherein the phone number is assigned from a carrier of the user and the virtual number is assigned from a TRS provider to the user; and a communications device of the user which includes a phone call unit associated with the phone number and a TRS call unit associated with the virtual number.

Abstract: Provided are integrated circuits and methods for transposing a tensor using processing element array operations. In some cases, it may be necessary to transpose elements of a tensor to perform a matrix operation. The tensor may be decomposed into blocks of data elements having dimensions consistent with the dimensions of a systolic array. An identity multiplication may be performed on each block of data elements loaded into a systolic array and the multiplication products summed in column partitions of a results buffer. The data elements in the column partitions of results buffer can then be mapped to row partitions of a buffer memory for further processing.

Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.

Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.

Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.

Abstract: Techniques are disclosed for debugging a neural network execution on a target processor. A reference processor may generate a plurality of first reference tensors for the neural network. The neural network may be repeatedly reduced to produce a plurality of lengths. For each of the lengths, a compiler converts the neural network into first machine instructions, the target processor executes the first machine instructions to generate a first device tensor, and the debugger program determines whether the first device tensor matches a first reference tensor. A shortest length is identified for which the first device tensor does not match the first reference tensor. Tensor output is enabled for a lower-level intermediate representation of the shortest neural network, and the neural network is converted into second machine instructions, which are executed by the target processor to generate a second device tensor.

Abstract: A method of manufacturing a polycrystalline silicon layer for a display device includes the steps of forming an amorphous silicon layer on a substrate, cleaning the amorphous silicon layer with hydrofluoric acid, rinsing the amorphous silicon layer with hydrogenated deionized water, and irradiating the amorphous silicon layer with a laser beam to form a polycrystalline silicon layer.

Abstract: The present disclosure relates to a display system including a capsule image view, a 3D mini-map, and a 3D panoramic view, and a method of generating a 3D panoramic view. Specifically, according to the present disclosure, it is possible to infer the shape of an organ using a 3D mini-map and to simultaneously identify whether or not the capsule endoscope captures the images, and information on the position and posture of the capsule endoscope at primary captured points by visualizing the actual movement path of the capsule endoscope, thereby improving the accuracy of examination, and since multiple 2D images captured by a single capsule endoscope are able to be viewed as a single 3D panoramic image without changing the structure of the capsule endoscope, it is economical and the viewing angle of the image is able to be increased, thereby reducing the examination time and fatigue of the examiner.

Abstract: An embodiment provides a manufacturing method of a polycrystalline silicon layer, including: forming a first amorphous silicon layer on a substrate; doping an N-type impurity into the first amorphous silicon layer; forming a second amorphous silicon layer on the n-doped first amorphous silicon layer; doping a P-type impurity into the second amorphous silicon layer; and crystalizing the n-doped first amorphous silicon layer and the p-doped second amorphous silicon layer by irradiating a laser beam onto n-doped first amorphous silicon layer and the p-doped second amorphous silicon layer to form a polycrystalline silicon layer.

Abstract: Proposed is a technology related to the ionization of silicon, and more particularly, to a technology for ionization by organizing silicon using a water-soluble silicate with a tricarboxylic acid or a dicarboxylic acid. This technology enables preparation and use of products containing an organized silicon ion complex in a variety of applications including foods such as water and beverages and medical products, as well as electrochemical applications. In particular, it is expected to treat and prevent various diseases caused by silicon deficiency by providing an organized form of silicon that does not exist as an ion in nature.

Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.

Abstract: Disclosed in the present invention is a low-temperature cooking machine. The low-temperature cooking machine comprises a flexible heating unit and a pump, and the pump is used for providing pressure or suction to cause the flexible heating unit to deform and contact and heat food. The low-temperature cooking machine in the present invention is a novel cooking device; under the action of the pump, the flexible heating unit as a heater can be deformed and directly contact food, so as to directly heat and cook the food. The low-temperature cooking machine in the present invention is a novel device and can replace an existing low-temperature cooking device having a constant temperature water bath and a vacuum plastic package machine.

Abstract: The present invention relates to a manufacturing device for manufacturing a large amount of micro-scaffolds for a long period of time such that stable and uniform particles can be fabricated. The manufacturing device comprises: a first solution storage portion for storing a polymer support structure solution; a second solution storage portion for storing an emulsifier solution; a gas storage portion connected to each of the first solution storage portion and the second solution storage portion; a pressure control portion for controlling the pressure of the transporting gas flowing into the first solution storage portion and the second solution storage portion from the pressurization portion, respectively; a scaffold injector portion for receiving the polymer support structure solution and the emulsifier solution provided by the transporting gas, respectively; and a scaffold generating portion for receiving the scaffold dispersion discharged through the scaffold injection portion.

Abstract: A display device and a method of manufacturing a display device are provided. A display device includes a lower conductive pattern disposed on a substrate, a lower insulating layer disposed on the lower conductive pattern, the lower insulating layer including a first lower insulating pattern including an overlapping region overlapping the lower conductive pattern, and a protruding region. The display device includes a semiconductor pattern disposed on the first lower insulating pattern and having a side surface, the side surface being aligned with a side surface of the first lower insulating pattern or disposed inward from the side surface of the first lower insulating pattern, a gate insulating layer disposed on the semiconductor pattern, a gate electrode disposed on the gate insulating layer, and an empty space disposed between the substrate and the protruding region of the first lower insulating pattern.

Abstract: A printer includes a printing unit to form a toner image on a printing medium, a fuser to apply heat and pressure to the printing medium that has passed through the printing unit to fuse the toner image on the printing medium, and a liquid-vapor chamber having a length in a width direction of the printing medium greater than a width of the printing medium. The liquid-vapor chamber has a heat absorber side to face the printing medium to absorb heat from the printing medium, a condenser side apart from the heat absorber side in an opposite direction not facing the printing medium to form an inner space between the condenser side and the heat absorber side, and a working fluid sealed in the inner space and to undergo a liquid-vapor phase change by moving between the heat absorber side and the condenser side, to absorb heat from the printing medium to cool the printing medium that has passed through the fuser.

Abstract: A method of manufacturing a polycrystalline silicon layer for a display device includes the steps of forming an amorphous silicon layer on a substrate, cleaning the amorphous silicon layer with hydrofluoric acid, rinsing the amorphous silicon layer with hydrogenated deionized water, and irradiating the amorphous silicon layer with a laser beam to form a polycrystalline silicon layer.

Abstract: A self-aligned p+ contact MOSFET device is provided. A process to manufacture the device includes forming oxide plugs on top of gate trenches, conducting uniform silicon mesa etch back, and forming oxide spacers to form contact trenches.

Abstract: The present invention relates to a medical robot system capable of effectively removing a calcified thrombus in a blood vessel. The present invention proposes a new guide-wired helical microrobot for mechanical thrombectomy applied to a calcified thrombus. Also, the present invention proposes an electromagnetic navigation system (ENS) which uses a high frequency operation that is based on a resonant effect in order to enhance the boring force of a microrobot. The microrobot system of the present invention can precisely tunnel through a blood vessel blockage site by means of the electromagnetic navigation system without damaging blood vessel walls. The microrobot system of the present invention has a wide range of applications including not only for thrombosis, but also thromboangiitis obliterans caused by vasoocclusion, cerebral infarction, strokes, angina or myocardial infarction, peripheral artery occlusive disease, or atherosclerosis, etc.

Abstract: The present invention proposes a radiation detector including a housing, a radiation detection panel accommodated in the housing and converting radiation incident from the outside of the housing into an electric signal, a printed circuit board electrically connected to the radiation detection panel and an intermediate plate that is disposed between the radiation detection panel and the printed circuit board, supports the radiation detection panel, and is electrically connected to the ground line of the printed circuit board, wherein the intermediate plate is transmissive to the radiation.