Abstract: The present invention provides a silicon carbide Schottky-barrier diode device and a method for manufacturing the same. The silicon carbide Schottky bather diode device includes a primary n? epitaxial layer, an n+ epitaxial region, and a Schottky metal layer. The primary n? epitaxial layer is deposited on an n+ substrate joined with an ohmic metal layer at an undersurface thereof. The n+ epitaxial region is formed by implanting n+ ions into a central region of the primary n? epitaxial layer. The Schottky metal layer is deposited on the n+ epitaxial layer.

Abstract: Disclosed is a method for fabricating a semiconductor device including: sequentially forming a first insulating film and a first barrier layer on a first surface of a substrate; etching the first barrier layer to form a first barrier layer pattern; etching the first insulating film to form a first insulating film pattern; removing the first barrier layer pattern and forming a first type epitaxial layer on an exposed first portion of the substrate; forming a second insulating film and a second barrier layer on the first type epitaxial layer and the first insulating film pattern; etching the second barrier layer to form a second barrier layer pattern; etching the second insulating film to form a second insulating film pattern, and etching the first insulating film pattern; and forming a second type epitaxial layer on an exposed second portion of the first surface of the n substrate.

Abstract: A schottky barrier diode includes: an n? type epitaxial layer that is disposed at a first surface of an n+ type silicon carbide substrate; a plurality of n type pillar areas that are disposed at the inside of the n? type epitaxial layer and that are disposed at a first portion of the first surface of the n+ type silicon carbide substrate; a p type area that is disposed at the inside of the n? type epitaxial layer and that is extended in a direction perpendicular to the n type pillar areas; a plurality of p+ areas in which the n? type epitaxial layer is disposed at a surface thereof and that are separated from the n type pillar areas and the p type area; a schottky electrode that is disposed on the n? type epitaxial layer and the p+ areas; and an ohmic electrode that is disposed at a second surface of the n+ type silicon carbide substrate.

Abstract: A semiconductor device structure for an ohmic contact is provided, including a silicon carbide substrate and an ohmic contact layer disposed on the silicon carbide substrate. A carbon layer is disposed on the ohmic contact layer. An anti-diffusion layer is disposed on the carbon layer, and a pad layer is disposed on the anti-diffusion layer. The anti-diffusion layer is made of any one of tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN).

Abstract: The present inventive concept has been made in an effort to improve the breakdown voltage of a silicon carbide MOSFET using a trench gate. A semiconductor device according to the present inventive concept includes a p type pillar region disposed below the trench, spaced apart from the trench or a first p type pillar region and a second p type pillar region disposed below the trench and corresponding to two corners of the trench.

Abstract: The present inventive concept has been made in an effort to increase the width of a channel in a silicon carbide MOSFET using a trench gate. According to the exemplary embodiment of the present inventive concept, the width of a channel can be increased, compared with the conventional art, by forming a plurality of protrusions extending to the p type epitaxial layer on both sides of the trench.

Abstract: A semiconductor device includes an n+ type silicon carbide substrate; a plurality of n type pillar regions, a plurality of p type pillar regions, and an n? type epitaxial layer disposed on a first surface of the n+ type silicon carbide substrate; a p type epitaxial layer and an n+ region sequentially disposed on the n? type epitaxial layer; a trench penetrating the n+ region and the p type epitaxial layer and disposed on the n? type epitaxial layer; a gate insulating film disposed within the trench; a gate electrode disposed on the gate insulating film; an oxide film disposed on the gate electrode; a source electrode disposed on the p type epitaxial layer, the n+ region, and the oxide film; and a drain electrode positioned on a second surface of the n+ type silicon carbide substrate.

Abstract: Disclosed is a method for fabricating a semiconductor device including: sequentially forming a first insulating film and a first barrier layer on a first surface of a substrate; etching the first barrier layer to form a first barrier layer pattern; etching the first insulating film to form a first insulating film pattern; removing the first barrier layer pattern and forming a first type epitaxial layer on an exposed first portion of the substrate; forming a second insulating film and a second barrier layer on the first type epitaxial layer and the first insulating film pattern; etching the second barrier layer to form a second barrier layer pattern; etching the second insulating film to form a second insulating film pattern, and etching the first insulating film pattern; and forming a second type epitaxial layer on an exposed second portion of the first surface of the n substrate.

Abstract: A Schottky barrier diode includes: an n+ type silicon carbide substrate; an n? type epitaxial layer disposed on a first surface of the n+ type silicon carbide substrate and includes an electrode area and a terminal area positioned outside of the electrode area; a first trench and a second trench disposed on the n? type epitaxial layer in the terminal area; a p area disposed under the first trench and the second trench; a Schottky electrode disposed on the n? type epitaxial layer in the electrode area; and an ohmic electrode disposed on a second surface of the n+ type silicon carbide substrate, wherein the first trench and the second trench are adjacently positioned to form a step.

Abstract: A schottky barrier diode includes an n? type epitaxial layer disposed at a first surface of an n+ type silicon carbide substrate, a plurality of n type pillar areas disposed in the n? type epitaxial layer at a first portion of a first surface of the n+ type silicon carbide substrate, a plurality of p+ areas disposed at a surface of the n? type epitaxial layer and separated from the n type pillar area, a schottky electrode disposed on the n? type epitaxial layer and the p+ area, and an ohmic electrode disposed at a second surface of the n+ type silicon carbide substrate. A doping density of the n type pillar area is larger than a doping density of the n? type epitaxial layer.

Abstract: A semiconductor device includes: a plurality of n type pillar regions and an n? type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate; a p type epitaxial layer and an n+ region disposed on the plurality of n type pillar regions and the n? type epitaxial layer; a trench penetrating the n+ region and the p type epitaxial layer and disposed on the plurality of n type pillar regions and the n? type epitaxial layer; a gate insulating film disposed within the trench; a gate electrode disposed on the gate insulating film; an oxide film disposed on the gate electrode; a source electrode disposed on the p type epitaxial layer, the n+ region, and the oxide film; and a drain electrode disposed on a second surface of the n+ type silicon carbide substrate, wherein each corner portion of the trench is in contact with a corresponding n type pillar region.

Abstract: A method for fabricating a semiconductor device includes: sequentially forming an n? type epitaxial layer, a p type epitaxial layer, and a first n+ region on a first surface of an n+ type silicon carbide substrate; forming a trench by penetrating the first n+ region and the p type epitaxial layer, and etching part of the n? type epitaxial layer; forming a buffer layer in the trench and on the first n+ region; etching the buffer layer to form a buffer layer pattern on both sidewalls defined by the trench; forming a first silicon film on the first n+ region, the buffer layer pattern, and a surface of the n? type epitaxial layer exposed by the trench; oxidizing the first silicon film to form a first silicon oxide film; removing the buffer layer pattern by an ashing process to form a first silicon oxide film pattern; forming a second silicon film on the first silicon oxide film pattern and in the trench; oxidizing the second silicon film to form a second silicon oxide film; and etching the second silicon oxide fi

Abstract: A method of manufacturing a semiconductor device includes sequentially forming an n? type epitaxial layer, a p type epitaxial layer, and a first n+ region on a first surface of an n+ type silicon carbide substrate, and forming a trench through the first n+ region and the p type epitaxial layer, wherein the forming of the trench includes forming a photosensitive layer pattern on the first n+ region, etching the first n+ region and the p type epitaxial layer by using the photosensitive layer pattern as a mask, forming a buffer layer by using amorphous carbon on the first n+ region after the photosensitive layer pattern is removed, forming a buffer layer pattern by etching the buffer layer, etching using the buffer layer pattern as the mask, isotropically etching to form a second portion of the trench, and removing the buffer layer pattern.

Abstract: Disclosed herein is a semiconductor device and method of manufacturing the semiconductor, including an n type buffer layer disposed on a first surface of an n+ type silicon carbide substrate, an n? type epitaxial layer disposed on the n type buffer layer, a first type of trench disposed on each side of a second type of trench, wherein the trenches are disposed in the n? type epitaxial layer, an n+ region disposed on the n? type epitaxial layer, a p+ region disposed in each first type of trench, a gate insulating layer disposed in the second trench, a gate material disposed on the gate insulating layer, an oxidation layer disposed on the gate material, a source electrode disposed on the n+ region, oxidation layer, and p+ region, and a drain electrode disposed on a second surface of the n+ type silicon carbide substrate.

Abstract: A schottky barrier diode may include a first n? type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate, a first p+ region disposed in the first n? type epitaxial layer, a second n type epitaxial layer disposed on the first n? type epitaxial layer and the first p+ region, a second p+ region disposed in the second n type epitaxial layer, a schottky electrode disposed on the second n type epitaxial layer and the second p+ region, and an ohmic electrode disposed on a second surface of the n+ type silicon carbide substrate, wherein the first p+ region and the second p+ region may be in contact with each other.

Abstract: Disclosed is an LDMOS device, which is configured to reduce an electric field concentrated to a gate oxide film and lower an ON-resistance produced when the device conducts a forward action, and a method for manufacturing the same. More specifically, when an n-drift region is formed on a P-type substrate, a p-body is formed on the n-drift region through an epitaxial process, and then the p-body region is partially etched to form a plurality of p-epitaxial layers, so that when the device executes an action for blocking a reverse voltage, depletion layers are formed between the junction surfaces of the p-epitaxial layers and the n-drift region including the junction surfaces between the n-drift region and the p-body.

Abstract: A method and system to compress and decode mesh data with random accessibility in a three-dimensional mesh model, the system to compress mesh data with random accessibility in a three-dimensional mesh model including: a mesh data acquisition unit to acquire mesh data from a three-dimensional mesh model having a plurality of cells; a wire mesh generation unit to generate a wire mesh including a plurality of wire cells by using the mesh data, each wire cell including at least two cells of the plurality of cells; a data structure generation unit to generate wire mesh information on the wire mesh and wire cell data including mesh data of the respective wire cells; and an encoding unit to compress the generated wire mesh information and the generated wire cell data.

Abstract: A method of manufacturing a semiconductor device may include forming a first n? type epitaxial layer by performing a first epitaxial growth on a first surface of an n+ type silicon carbide substrate, forming a photosensitive layer pattern on the first n? type epitaxial layer, etching the first n? type epitaxial layer by using the photosensitive layer pattern as a mask to form a first trench, forming a buffer layer on the first n? type epitaxial layer after the photosensitive layer pattern may be removed, etching the buffer layer to form a trench passivation layer in the first trench, forming an n? type epitaxial layer by performing a second epitaxial growth on the first n? type epitaxial layer, and forming a p type epitaxial layer by performing a third epitaxial growth on the n? type epitaxial layer other than the portion on which the trench passivation layer may be formed.

Abstract: A vehicle with independently driven multiple axles and a controller which independently drives the multiple axles are disclosed. The controller includes a first controller which determines a target control value including at least one of a mechanical steering angle of each of a plurality of wheels of a vehicle, a target yaw moment of the vehicle, a target longitudinal force of the vehicle, and a target wheel speed of each of the plurality of wheels, according to a driving condition of the vehicle, when the first controller receives an operation input including at least one of a steering input, an acceleration input and a braking input; and a second controller which determines wheel torques of the plurality of wheels, which drive the plurality of wheels independently, based on the target control value, wherein the wheel torques of the plurality of wheels are different from one another.

Abstract: Disclosed is an LDMOS device, which is configured to reduce an electric field concentrated to a gate oxide film and lower an ON-resistance produced when the device conducts a forward action, and a method for manufacturing the same. More specifically, when an n-drift region is formed on a P-type substrate, a p-body is formed on the n-drift region through an epitaxial process, and then the p-body region is partially etched to form a plurality of p-epitaxial layers, so that when the device executes an action for blocking a reverse voltage, depletion layers are formed between the junction surfaces of the p-epitaxial layers and the n-drift region including the junction surfaces between the n-drift region and the p-body.