Abstract: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide methods for manufacturing a semiconductor device, and semiconductor devices produced thereby, that comprise forming an interposer including a reinforcement layer.

Abstract: The present technology can include a semiconductor device assembly comprising an RDL with a top surface and a side surface intersecting the top surface. The assembly can further comprise a semiconductor device coupled to the top surfaces, and a mold material encasing the semiconductor device (when included) and directly coupled to at least a portion of the top surface and the side surface of the RDL. In other embodiments, the assembly can comprise an RDL with a top surface, a bottom surface opposite thereto, and a sloped side surface extending between the top surface and the bottom surface. The assembly similarly can further comprise a semiconductor device coupled to the top surface, and a mold material encasing the semiconductor device and directly coupled to at least a portion of the top surface and the side surface of the RDL.

Abstract: Stacked die modules for semiconductor device assemblies and methods of manufacturing the modules are disclosed. In some embodiments, the module includes a shingled stack of semiconductor dies, each die having an uncovered porch with bond pads. Further, a dielectric structure partially encapsulates the shingled stack of semiconductor dies. The dielectric structure includes openings corresponding to the bond pads. The module also includes conductive structures disposed on the dielectric structure, where each of the conductive structures extends over at least one porch of the semiconductor dies to connect to at least one bond pad through a corresponding opening. The semiconductor device assembly may include a controller die attached to a package substrate, the controller die carrying one or more stacked die modules, and bonding wires connecting terminals of the modules to package bond pads.

Abstract: Stacked semiconductor dies for semiconductor device assemblies and associated methods and systems are disclosed. In some embodiments, the semiconductor die assembly includes a substrate with a first opening in an inner portion and a second opening in an outer portion of the substrate. Further, the semiconductor die assembly can include a master die attached to a front side of the substrate, where the master die includes a first bond pad proximate to the first opening and a second bond pad proximate to the second opening. The first and second bond pads of the master die can be coupled with first and second substrate bond pads on a back side of the substrate, opposite to the front side, using first and second bonding wires extending through the first and second openings, respectively.

Abstract: A semiconductor device and manufacturing method thereof. Various aspects of the disclosure may, for example, comprise forming a back end of line layer on a dummy substrate, completing at least a first portion of an assembly, and removing the dummy substrate.

Abstract: This document discloses techniques, apparatuses, and systems for a semiconductor device with a porous air vent. The semiconductor device includes a semiconductor die mounted to a substrate at one or more contact pads. Underfill material is disposed between the semiconductor die and the substrate. The substrate includes a porous portion composed of a porous material. The porous material is such that air, but not the underfill material, may pass from an area between the semiconductor die and the substrate to an area below the substrate. As a result, air may pass through the porous portion during the underfill process and the underfill material may be retained.

Abstract: Semiconductor device assemblies can include a substrate having a substrate contact. The assemblies can include a first semiconductor device and a second semiconductor device arranged in a face-to-face configuration. The assemblies can include a fan-out porch on the substrate at a lateral side of the first semiconductor device and including a wirebond contact, the wirebond contact being electrically coupled to the first semiconductor device. The assemblies can include a wirebond operably coupling the wirebond contact to the substrate contact. The assemblies can include a pillar or bump operably coupling the active side of the first semiconductor device to the active side of the second semiconductor device. In some embodiments, the wirebond contact is operably couple to the active side of the first semiconductor device.

Abstract: A wafer level fan out semiconductor device and a manufacturing method thereof are provided. A first sealing part is formed on lateral surfaces of a semiconductor die. A plurality of redistribution layers are formed on surfaces of the semiconductor die and the first sealing part, and solder balls are attached to the redistribution layers. The solder balls are arrayed on the semiconductor die and the first sealing part. In addition, a second sealing part is formed on the semiconductor die, the first sealing part and lower portions of the solder balls. The solder balls are exposed to the outside through the second sealing part. Since the first sealing part and the second sealing part are formed of materials having thermal expansion coefficients which are the same as or similar to each other, warpage occurring to the wafer level fan out semiconductor device can be suppressed.

Abstract: A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device structure (e.g., a sensor device structure), and method for manufacturing thereof, that comprises a three-dimensional package structure free of wire bonds, through silicon vias, and/or flip-chip bonding.

Abstract: A semiconductor device assembly is provided, including a substrate having a top side and a bottom side opposite the top side; a contact pad formed at the top side of the substrate; an under bump metallization (UBM) structure disposed laterally offset from the contact pad; a redistribution layer electrically coupling the contact pad and the UBM structure; a copper ball electrically coupled to the UBM structure by a solder material; and a molding compound disposed over the redistribution structure and at least partially surrounding the copper ball.

Abstract: Semiconductor device assemblies with improved ground connections, and associated systems and methods are disclosed. In one embodiment, a semiconductor device assembly may include one or more semiconductor dies mounted on an upper surface of a package substrate. Further, the package substrate includes a bond pad disposed on the upper surface, which may be designated as a ground node for the semiconductor device assembly. The bond pad may be electrically connected to an electromagnetic interference (EMI) shield of the semiconductor device assembly through a conductive component attached to the bond pad and configured to be in contact with the EMI shield at a sidewall surface or a top surface of the semiconductor device assembly, thereby forming the ground connection. Such ground connection may reduce a processing time to form the EMI shield while improving yield and reliability performance of the semiconductor device assemblies.

Abstract: Semiconductor device assemblies can include a substrate having a substrate contact. The assemblies can include a first semiconductor device and a second semiconductor device arranged in a face-to-face configuration. The assemblies can include a fan-out porch on the substrate at a lateral side of the first semiconductor device and including a wirebond contact, the wirebond contact being electrically coupled to the first semiconductor device. The assemblies can include a wirebond operably coupling the wirebond contact to the substrate contact. The assemblies can include a pillar or bump operably coupling the active side of the first semiconductor device to the active side of the second semiconductor device. In some embodiments, the wirebond contact is operably couple to the active side of the first semiconductor device.

Abstract: The present technology is directed to methods of forming semiconductor dies with rabbeted regions. For example, the method can comprise forming a first channel along a street from a backside of the wafer to an intermediate depth between the backside of the wafer and a front side of the wafer. The first channel has a first sloped sidewall and a second sloped sidewall. A second channel is then formed by laser cutting from the intermediate depth in the wafer toward the front side of the wafer along a region between the first and second sidewalls of the first channel. The first sloped sidewall defines a rabbeted region at a side of the first semiconductor dies and the second sloped sidewall defines a rabbeted region at a side of the second semiconductor dies.

Abstract: A semiconductor device including a relatively thin interposer excluding a through silicon hole and a manufacturing method thereof are provided. The method includes forming an interposer on a dummy substrate. The forming of the interposer includes, forming a dielectric layer on the dummy substrate, forming a pattern and a via on the dielectric layer, and forming a seed layer at the pattern and the via of the dielectric layer and forming a redistribution layer and a conductive via on the seed layer. A semiconductor die is connected with the conductive via facing an upper portion of the interposer, and the semiconductor die is encapsulated with an encapsulant. The dummy substrate is removed from the interposer. A bump is connected with the conductive via facing a lower portion of the interposer.

Abstract: A semiconductor device with redistribution layers on partial encapsulation is disclosed and may include providing a carrier with a non-photosensitive protection layer, forming a pattern in the non-photosensitive protection layer, providing a semiconductor die with a contact pad on a first surface, and bonding the semiconductor die to the non-photosensitive protection layer such that the contact pad aligns with the pattern formed in the non-photosensitive protection layer. A second surface opposite to the first surface of the semiconductor die, side surfaces between the first and second surfaces of the semiconductor die, and a portion of a first surface of the non-photosensitive protection layer may be encapsulated with an encapsulant. The carrier may be removed leaving the non-photosensitive protection layer bonded to the semiconductor die. A redistribution layer may be formed on the contact pad and a second surface of the non-photosensitive protection layer opposite to the first surface.

Abstract: A mold chase for packaging a compartmentally shielded multifunctional semiconductor is provided. The mold chase generally includes a first cavity and a second cavity separated by a trench plate positioned between a first component and a second component of the multifunctional semiconductor between which a compartmental shield is required. The mold chase is lowered into a molding position over the multifunctional semiconductor and a molding material is injected through an inlet sprue into the first and second cavities to surround the first and second components, respectively. After the molding material is cured, the mold chase is removed and an open trench is formed in the cured molding material by the trench plate. The open trench is filled with a conductive material to form the compartmental shield. A conformal shield may be added to cover the package.

Abstract: Semiconductor device assemblies can include a substrate having a substrate contact. The assemblies can include a first semiconductor device and a second semiconductor device arranged in a face-to-face configuration. The assemblies can include a fan-out porch on the substrate at a lateral side of the first semiconductor device and including a wirebond contact, the wirebond contact being electrically coupled to the first semiconductor device. The assemblies can include a wirebond operably coupling the wirebond contact to the substrate contact. The assemblies can include a pillar or bump operably coupling the active side of the first semiconductor device to the active side of the second semiconductor device. In some embodiments, the wirebond contact is operably couple to the active side of the first semiconductor device.

Abstract: Stacked die modules for semiconductor device assemblies and methods of manufacturing the modules are disclosed. In some embodiments, the module includes a shingled stack of semiconductor dies, each die having an uncovered porch with bond pads. Further, a dielectric structure partially encapsulates the shingled stack of semiconductor dies. The dielectric structure includes openings corresponding to the bond pads. The module also includes conductive structures disposed on the dielectric structure, where each of the conductive structures extends over at least one porch of the semiconductor dies to connect to at least one bond pad through a corresponding opening. The semiconductor device assembly may include a controller die attached to a package substrate, the controller die carrying one or more stacked die modules, and bonding wires connecting terminals of the modules to package bond pads.

Abstract: A semiconductor device including a relatively thin interposer excluding a through silicon hole and a manufacturing method thereof are provided. The method includes forming an interposer on a dummy substrate. The forming of the interposer includes, forming a dielectric layer on the dummy substrate, forming a pattern and a via on the dielectric layer, and forming a seed layer at the pattern and the via of the dielectric layer and forming a redistribution layer and a conductive via on the seed layer. A semiconductor die is connected with the conductive via facing an upper portion of the interposer, and the semiconductor die is encapsulated with an encapsulant. The dummy substrate is removed from the interposer. A bump is connected with the conductive via facing a lower portion of the interposer.

Abstract: A mold chase for packaging a compartmentally shielded multifunctional semiconductor is provided. The mold chase generally includes a first cavity and a second cavity separated by a trench plate positioned between a first component and a second component of the multifunctional semiconductor between which a compartmental shield is required. The mold chase is lowered into a molding position over the multifunctional semiconductor and a molding material is injected through an inlet sprue into the first and second cavities to surround the first and second components, respectively. After the molding material is cured, the mold chase is removed and an open trench is formed in the cured molding material by the trench plate. The open trench is filled with a conductive material to form the compartmental shield. A conformal shield may be added to cover the package.