Patents by Inventor Jong Tae Kim

Jong Tae Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020179685
    Abstract: Disclosed herein is a lead bonding method for SMD packages. The lead bonding method includes the step of placing a package body with its lead-positioning surface facing upward. A lead with solder is arranged on the lead-positioning surface of the package body using vision system. The lead is spot-welded onto the package body to fix the lead to the package body. The package body spot-welded together with the lead is arranged in a positioning depression of a jig with the lead facing downward. The solder formed on the lead are melted to bond the lead to the package body.
    Type: Application
    Filed: July 27, 2001
    Publication date: December 5, 2002
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jong-Sung Jung, Jong-Tae Kim, Guem-Young Youn, Chang-Dug Kim
  • Patent number: 5943558
    Abstract: A method of making an assembly package having an air tight cavity for housing an electronic element such as a GaAs semiconductor chip. The method includes the formation of a dielectric base by placing a placing a conductive lead frame comprising a frame pad and a plurality of conductive leads inside a die having a top interior surface and a bottom interior surface, injecting a thermally setting liquefied epoxy into die cavity, curing the epoxy and removing the die. The die includes at least one post which protrudes toward the die's top interior surface such that the top surface of the post presses the inner end of each of said plurality of conductive leads against the top interior surface of the die, and also includes a pin protruding from the die's top interior surface toward the post's top surface. The post firmly holds the conductive leads in a common level plane during the injection of the epoxy into the cavity while the use of the pin results in a the formation of a pin hole in the dielectric base.
    Type: Grant
    Filed: September 23, 1996
    Date of Patent: August 24, 1999
    Assignees: Communications Technology, Inc., CTI Semiconductor Corporation
    Inventors: Jong Tae Kim, Chan Ik Park
  • Patent number: 5801074
    Abstract: A method of making an assembly package having an airtight cavity for housing an electrical element, such as a semiconductor chip. The method includes bonding a shell to a conductive base with a thermally setting alpha-staged epoxy resin which is characterized as being a gel in the uncured state at room temperature. The use of the alpha-staged epoxy resin, in contrast with the conventional beta-staged epoxy resin, results in an airtight cavity being formed without punctures or fissures in the epoxy resin. The method also provides a two-step heating process whereby the epoxy resin is cured at a first elevated temperature in the open atmosphere and further cured and stabilized at a second elevated temperature in a closed environment.
    Type: Grant
    Filed: February 20, 1996
    Date of Patent: September 1, 1998
    Inventors: Jong Tae Kim, Chau Ik Park, Chang Hyung Lee
  • Patent number: 5778520
    Abstract: A method of making an assembly having an air tight cavity for holding an element therein and having a plurality of thin and flat planar conductive leads extending outwardly from the cavity for providing electrically conductive paths from the element held within the cavity, and a conductive plate for supporting the circuitry, comprising (a) injecting a liquified thermosetting epoxy into a die and solidifying the epoxy by heat curing to form a dielectric frame that is configured such that the inner end and tip portions of the conductive leads are buried in the frame, the flat surfaces of the intermediate portions of the conductive leads are exposed in a common plane and the outer end portions of the conductive leads extend outside the epoxy, (b) bonding the bottom surface of the resulting dielectric frame to the outer periphery of the conductive base plate, (c) plating the exposed flat surfaces of the conductive leads and the conductive base plate with a conductive material, (d) connecting the circuitry dispose
    Type: Grant
    Filed: July 3, 1996
    Date of Patent: July 14, 1998
    Inventors: Jong Tae Kim, Chan Ik Park