Abstract: A method for forming a silicon nitride/silicon oxide (NO) layer within a microelectronics fabrication, and the microelectronics fabrication having the silicon nitride/silicon oxide (NO) layer formed therein. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a first silicon nitride layer through a first deposition method. There is then formed upon the first silicon nitride layer a second silicon nitride layer through a second deposition method. Finally, there is annealed thermally in an oxidizing environment the first silicon nitride layer and the second silicon nitride layer to form therefrom a silicon nitride/silicon oxide (NO) layer.

Abstract: A process and structure are described wherein logic and memory share the same chip. Contacts to the memory circuits are made using the SAC process, thus ensuring maximum density, while contacts to the logic circuits are made using the SALICIDE process, thus ensuring high performance. The two processes have been integrated within a single chip by first depositing the various layers needed by the gate pedestals in both the logic and the memory areas and then forming the two sets of gate pedestals in separate steps. Gates located in the logic area are formed only from polysilicon while those located in the memory areas also have an overlay of tungsten silicide topped by a hard mask of silicon nitride. With the two sets of gates in place, source/drain regions are formed in the usual way. This includes growing of silicon nitride spacers on the vertical sides of the pedestals. The pedestals in the memory area are much longer than those in the logic area since they extend all the way to the top of the hard masks.

Abstract: A process for forming a crown shaped, storage node structure, for a DRAM capacitor structure, with a roughened top surface topology, needed for increased surface area, has been developed. The process features the use of a tungsten silicide layer, used as a component of the storage node structure, with the tungsten silicide layer, subjected to subsequent procedures, providing the roughened top surface topology for the storage node structure. The tungsten silicide layer, after deposition, is subjected to an oxidation procedure, followed by removal of the formed oxide layer, from a bottom portion of unoxidized tungsten silicide layer, resulting in the desired, roughened top surface topology, of the bottom portion of unoxidized tungsten silicide.

Abstract: A method for forming an anti-reflective-coating(ARC) layer is described. This ARC layer performs not only in its capacity to reduce reflections from its subjacent metal layer during the metal patterning photoresist exposure, but also serves as an effective etch inhibitor during subsequent via etching. Of particular importance is the ability provided by this ARC layer to sustain its etch resistance during considerable over etching such as is required when vias of different depths are to be opened. The ARC layer differs from the conventional titanium nitride ARC layer in that it has a base layer of titanium below the titanium nitride portion. It is this titanium layer and an optional intermediate Ti rich layer that sustains the over etch. Additionally, the titanium forms an improved bonding with the metal beneath providing reduced via contact resistance and greater via stability and consistency.

Abstract: A method for providing a chemical mechanical polishing planarization process for preventing multi-polysilicon and multi-metal level electrical shorts, which includes briefly the sequential processing steps of i) providing an insulating layer to a first thickness over a device wafer with non-planar surface topography; ii) chemical-mechanical polishing the first insulating layer; and iii) deposition of another polysilicon layer of second thickness to prevent the barely exposed or exposed underlying polysilicon from shorting to the next polysilicon or metal level of interconnects.

Abstract: The present invention discloses a method for making low-topography buried capacitor including the steps of first depositing oxide layers, and then forming a small pre-contact hole by a dry etch method and a large contact hole by a wet etch method while using silicon nitride caps and sidewall spacers previously deposited on the word lines and on the bit lines as etch stop layers. A buried capacitor that has significantly improved topography can be fabricated in a semiconductor device.

Abstract: The present invention is an orientation flat aligner for preventing the angle deviation of the flat edge of the wafer. This invention applies two new designs to the aligner: (1) The two parallel rollers with different radius instead of two parallel rollers the same radii prevent the problem of the angle deviation to line up the flat edge of the wafer. (2) placing the photosensor on the orientation flat aligner instead of on the sensor bracket avoids the detection error because of the photosensor position relate to the orientation flat aligner position and saves time on checking whether the flat edge of the wafer line up or not.

Abstract: A procedure for the installation of clean room processing tools which require rough pumping equipment located in areas outside of the clean room. Instead of simultaneously installing and testing the pumping equipment and the processing tool, the pumping equipment is installed first along with its associated support services. Foreline piping, terminating in the proximity of the processing tool vacuum port is also installed and capped off at this time. Functional testing and qualification of the rough pumping equipment is done and then the processing tool is moved into place and connected to the pumping line on the clean room floor. This independent and sequential installation procedure reduces perturbations of on-going manufacturing activity in the clean room area and also minimizes the risk of costly damage to the processing tool by faulty, un-tested, pumping equipment.

Abstract: A three dimensional polysilicon resistor and a method by which the three dimensional polysilicon resistor is manufactured. A semiconductor substrate has formed upon its surface an insulating layer. The insulating layer has a minimum of one aperture formed at least partially through the insulating layer. A polysilicon layer is formed upon the insulating layer and formed conformally into the aperture(s) within the insulating layer. The polysilicon layer is then patterned to form a resistor which includes the portion of the polysilicon layer which resides within the aperture(s).

Abstract: A method for increasing the surface area of a polysilicon storage node electrode, used as a component for a DRAM stacked capacitor structure, has been developed. The method features forming a metal silicide layer, on the top surface of the polysilicon storage node electrode, locally consuming regions of underlying polysilicon during the metal silicide formation. Removal of the metal silicide layer, from the surface of the polysilicon storage node electrode, results in a roughened surface, comprised of crevices in the top surface of the polysilicon storage node electrode, in regions in which localized metal silicide formation had occurred. The crevices in the top surface of the polysilicon storage node electrode result in surface area increases, when compared to counterparts fabricated using smooth polysilicon surfaces.

Abstract: A method and structure is described for a DRAM cell having a double wall tub shaped capacitor. The structure of the capacitor has two embodiments: a double wall tub shaped capacitor and a double wall cup shaped capacitor. In a first embodiment for the tub shaped capacitor, the method comprises using two masks to form a tub shaped hole partial through an insulating layer and a concentric contact hole over the source. A polysilicon layer is formed over the insulating layer. Oxide spacers are formed on the sidewalls of the tub shaped hole. The polysilicon layer is patterned to separate adjacent electrodes. Next, a polysilicon inner wall is formed on the spacer sidewalls. The oxide spacers are then removed. The dielectric and top electrode are formed next thus completing the double wall tub shaped capacitor. The second embodiment for forming the cup shaped capacitor comprises forming an insulating layer the substrate surface and forming a photoresist layer with an opening over a source region.

Abstract: A fabrication process for integrating stacked capacitor, DRAM devices, and thin film transistor, SRAM devices, has been developed. The fabrication process features combining key operations used to create transfer gate transistor structures, and access transistor structures for the DRAM and SRAM devices. In addition, process steps, used to create a capacitor structure, for the DRAM device, and a thin film transistor structure, for the SRAM device, are also shared. Another key feature of this invention is a buried contact structure, used for the SRAM device.

Abstract: Two embodiments of a method are described for fabricating a DRAM cell having a T or Y shaped capacitor connected to a MOS transistor with source and drain regions. In a first embodiment, the method comprises using two masks to form a cylindrical hole partial through the insulating layer and a concentric contact hole over the source. A first conductive layer is formed over the first insulating layer, at least completely filling the trench and filling the contact hole. In a key step, the first polysilicon layer is chemically mechanically polished thereby forming a T shaped storage electrode. Next, a capacitor dielectric layer and a top electrode are sequentially formed over at least the T shaped storage electrode. The second embodiment form the contact hole and trench as described above. A conformal first conductive layer is formed over the first insulating layer, filling the contact hole and covering the sidewalls and bottom of the trench, but not filling the trench.

Abstract: The present invention provides a method of manufacturing a cylindrical capacitor which has plug spacers that reduce capacitor size and increase overlay tolerances. The method begins by forming an insulating layer and a passivation layer over a substrate. A plug opening is formed through the passivation layer and the insulating layer. A polysilicon plug is formed in the plug opening. Plug opening spacers are formed on the sidewalls of the insulating and passivation layers in the plug opening. A first dielectric layer having a bottom electrode opening is formed over passivation layer and the plug is exposed. A third polysilicon layer is formed over the first dielectric layer and on the sidewalls of the first dielectric layer. A second dielectric layer is formed over the third polysilicon layer and in the bottom electrode opening. The second dielectric layer and the third polysilicon layer are RIE etched down to the level on the top surface of the first dielectric layer.

Abstract: In a telecommunications network, a method is provided for reading a desired telephone data record associated with a given telephone number from a line record database. Initially, a data processor reads data from an accessing data record stored in an index database. The accessing data record contains at least an accessing number designating a series of telephone numbers including the given telephone number, a pointer pointing to a data cluster in the line record database, and a blocking factor associated with the data cluster. The data cluster comprises a plurality of data nodes and includes all of the telephone data records associated with the series of telephone numbers designated by the accessing number. Each data node contains a number of individual telephone data records up to the blocking factor and a number of pointers each pointing to one of the number of individual telephone data records. The data processor accesses a data cluster based on the data read from the index database.

Abstract: A procedure for the installation of clean room processing tools which require rough pumping equipment located in areas outside of the clean room. Instead of simultaneously installing and testing the pumping equipment and the processing tool, the pumping equipment is installed first along with its associated support services. Foreline piping, terminating in the proximity of the processing tool vacuum port is also installed and capped off at this time. Functional testing and qualification of the rough pumping equipment is done and then the processing tool is moved into place and connected to the pumping line on the clean room floor. This independent and sequential installation procedure reduces perturbations of on-going manufacturing activity in the clean room area and also minimizes the risk of costly damage to the processing tool by faulty, un-tested, pumping equipment.

Abstract: A fabrication process for integrating stacked capacitor, DRAM devices, and thin film transistor, SRAM devices, has been developed. The fabrication process features combining key operations used to create transfer gate transistor structures, and access transistor structures for the DRAM and SRAM devices. In addition, process steps, used to create a capacitor structure, for the DRAM device, and a thin film transistor structure, for the SRAM device, are also shared. Another key feature of this invention is a buried contact structure, used for the SRAM device.

Abstract: The present invention provides a method of manufacturing a tub structured stacked capacitor having a central column for a dynamic random access memory (DRAM). The method uses only two photo masks to form the capacitor and a chemical mechanical polishing process to eliminate capacitor dielectric integrity problems. A first insulating layer having a contact opening is formed on a substrate. A first polysilicon layer is formed over the first insulation layer and fills the contact hole with polysilicon. Next, the first polysilicon layer over the first insulation layer is chemically mechanically polished to a depth that at least exposes the first insulation layer thereby forming a central vertical extension. An annular trench is formed in the insulating layer surrounding the central vertical extension. A second polysilicon layer and an oxide layer are formed over the trench, the central vertical extension, and the insulation layer.

Abstract: A method for fabricating buried metal plug structures for multi-polysilicon layer interconnects and for concurrently making metal plugs on semiconductor integrated circuits, such as DRAM and SRAM, was achieved. The method involved forming contact opening in an insulating layer over opening in a patterned polysilicon layer. The opening in the polysilicon layer aligned over source/drain contact areas on the substrate and providing a means for forming self-aligned contact openings. Buried metal plugs in the contact openings form interconnects between the polysilicon layer and the source/drains. And, by merging the process steps, concurrently forming metal plug interconnects for contacts to semiconductor devices and first level metal. The process is applicable to the formation of bit line contacts on DRAM and SRAM circuits and simultaneously form the peripheral contact on the chip.

Abstract: Reduced area metal contacts to a thin polysilicon layer contact structure having low ohmic resistance was achieved. The structure involves forming contact openings in an insulating layer over a buffer layer composed of a thick polysilicon layer. A portion of the sidewall in the opening includes a patterned thin polysilicon layer that forms part of a semiconductor device and also forms the electrical connection to the metal contact. The structure provides metal contacts having very low resistance and reduced area for increased device packing densities. The metal contact structure also eliminates the problem of forming P.sup.+ /N.sup.+ non-ohmic junctions usually associated with making P.sup.+ /N.sup.+ stacked contact. The structure further allows process steps to be used that provide larger latitude in etching the contact opening and thereby provides a structure that is very manufacturable.