Abstract: A semiconductor memory device and a method of fabricating the same are disclosed. The semiconductor memory device may include a conductive layer doped with impurities, a non-conductive layer on the conductive layer and undoped with impurities, an interlayer insulating film on the non-conductive layer and having a contact hole for exposing an upper surface of the non-conductive layer, an ohmic tungsten film on the contact hole, a lower portion of the ohmic tungsten film permeating the non-conductive layer to come in contact with the conductive layer, a tungsten nitride film on the contact hole on the ohmic tungsten film, and a tungsten film on the tungsten nitride film to fill the contact hole.

Abstract: Methods of forming a metal interconnection structure are provided. The methods include forming an insulating layer on a semiconductor substrate including a first metal interconnection. The insulating layer is patterned to form an opening that exposes the first metal interconnection. A first diffusion barrier layer is formed on the exposed first metal interconnection. After forming the first diffusion barrier layer, a second diffusion barrier layer is formed on the first diffusion barrier layer in the opening, the second diffusion barrier layer contacting a sidewall of the opening. A second metal interconnection is formed on the second diffusion barrier layer.

Abstract: A structure and formation method for electrically connecting aluminum and copper interconnections stabilize a semiconductor metallization process using an inner shape electrically connecting the aluminum and copper interconnections. To this end, a copper interconnection is disposed on a semiconductor substrate. An interconnection induction layer and an interconnection insertion layer are sequentially formed on the copper interconnection to have a contact hole exposing the copper interconnection. An upper diameter of the contact hole may be formed to be larger than a lower diameter thereof. A barrier layer and an aluminum interconnection are filled in the contact hole. The aluminum interconnection is formed not to directly contact the copper interconnection through the contact hole.

Abstract: An in-line annealing apparatus and a method of annealing a substrate using the in-line annealing apparatus in which a plurality of heating devices provide a transportation path of a substrate and heat the substrate transported along the transportation path to a crystallization temperature, and an instantaneous high-temperature annealing unit heats the substrate positioned in the transportation path between the heating devices to a instantaneous annealing temperature. The in-line annealing apparatus and the method of annealing a substrate using the same provide a highly efficient annealing process that can be performed at various temperatures including a high temperature of 700° C. or higher.

Abstract: A magnetron unit moving apparatus for preventing magnetization and magnetron sputtering equipment having the same. The magnetron unit moving apparatus includes a magnetron unit disposed adjacent to a target, to generate a specific magnetic field, and a movement unit to space the magnetron unit and the target apart such that a strength of a magnetic field generated over the target is within a predetermined reference strength range. It is possible to space the target and the magnetron unit apart so as to prevent the target from being magnetized when a process is not performed.

Abstract: A magnetic field generation control unit and a magnetron sputtering apparatus and method using the magnetic field generation control circuit. The magnetic field generation control unit includes a magnetic field generator for providing a specific magnetic field to a target consisting of a metal material to be deposited on a substrate, and a magnetic field generator control module electrically connected with the magnetic field generator, receiving an electrical signal from outside, and selectively supplying a current capable of generating the magnetic field to the magnetic field generator. The target is prevented from being magnetized when a sputtering process is not performed, and the magnetic field is generated from the target when the process is performed. Consequently, it is possible to perform uniform deposition on the substrate.

Abstract: A bonding pad structure for a semiconductor device includes a first lower metal layer beneath a second upper metal layer in a bonding region of the device. The lower metal layer is formed such that the metal of the lower metal layer is absent from the bonding region. As a result, if damage occurs to the structure during procedures such as probing or bonding at the bonding region, the lower metal is not exposed to the environment. Oxidation of the lower metal layer by exposure to the environment is prevented, thus improving reliability of the device.

Abstract: A semiconductor device includes a first interlayer dielectric including a trench on a semiconductor layer, a mask pattern on the first interlayer dielectric, a first conductive pattern in the trench, and a second interlayer dielectric on the mask pattern. The second interlayer dielectric includes an opening over the first conductive pattern. A second conductive pattern is in the opening and is electrically connected to the first conductive pattern. The first conductive pattern has an upper surface lower than an upper surface of the mask pattern.

Abstract: A method and apparatus for fabricating a vertical deposition mask capable of welding a mask sheet and a mask frame for preventing a large area mask from drooping due to the weight of the mask. The apparatus includes a tensioning device for tensioning a mask sheet and a welder for attaching a mask frame to a circumference of the mask sheet. The tensioning device includes clamps for supporting the mask sheet and tensioners coupled to the clamps for applying tensile force to the clamps and to evenly fix in place the mask sheet by the clamps.

Abstract: A gate structure is formed on a substrate. An insulating interlayer is formed covering the gate structure. The substrate is heat treated while exposing a surface of the insulating interlayer to a hydrogen gas atmosphere. A silicon nitride layer is formed directly on the interlayer insulating layer after the heat treatment and a metal wiring is formed on the insulating interlayer. The metal wiring may include copper. Heat treating the substrate while exposing a surface of the interlayer insulating layer to a hydrogen gas atmosphere may be preceded by forming a plug through the first insulating interlayer that contacts the substrate, and the metal wiring may be electrically connected to the plug. The plug may include tungsten.

Abstract: Methods of forming a semiconductor device that includes a diffusion barrier film are provided. The diffusion barrier film includes a metal nitride formed by using a MOCVD process and partially treated with a plasma treatment. Thus, a specific resistance of the diffusion barrier film can be decreased, and the diffusion barrier film may have distinguished barrier characteristics.

Abstract: A method of fabricating a semiconductor device is provided. The method includes providing a semiconductor substrate having a conductive pattern and forming an insulating layer on the conductive pattern and the semiconductor substrate. The insulating layer is patterned to form an opening which exposes a portion of the conductive pattern. A preliminary diffusion barrier layer is formed on an inner wall of the opening and a top surface of the insulating layer. Oxygen atoms are supplied onto the preliminary diffusion barrier layer to form a first diffusion barrier layer. A metal layer is formed on the first diffusion barrier layer. The metal layer is formed to fill the opening surrounded by the first diffusion barrier layer. A semiconductor device fabricated by the method and a semiconductor cluster tool used in fabrication of the semiconductor device are also provided.

Abstract: A conductive wiring for a semiconductor device is provided including a semiconductor substrate and a plurality of lower conductive structures on the semiconductor substrate. An insulating layer is provided that electrically insulates the plurality of lower conductive structures from one another. A first insulation interlayer pattern is provided on the insulation layer. The first insulation interlayer pattern includes a contact plug that contacts the substrate through the insulation layer. An etch-stop layer is provided on the contact plug and the first insulation interlayer pattern. A second insulation interlayer pattern is provided on the etch-stop layer. The second insulation interlayer pattern includes a conductive line that is electrically connected to the contact plug. Related methods and flash memory devices are also provided.

Abstract: An example embodiment provides a method of forming a conductive pattern in a semiconductor device. The method includes forming one or more dielectric layers over a first conductive pattern formed on a substrate; forming an opening in the one or more dielectric layers to expose a portion of the first conductive pattern, forming a growth promoting layer over the exposed portion of the first conductive pattern and the one or more dielectric layers, forming a growth inhibiting layer over a portion of the growth promoting layer, and forming the second conductive layer in the opening.

Abstract: A structure and formation method for electrically connecting aluminum and copper interconnections stabilize a semiconductor metallization process using an inner shape electrically connecting the aluminum and copper interconnections. To this end, a copper interconnection is disposed on a semiconductor substrate. An interconnection induction layer and an interconnection insertion layer are sequentially formed on the copper interconnection to have a contact hole exposing the copper interconnection. An upper diameter of the contact hole may be formed to be larger than a lower diameter thereof. A barrier layer and an aluminum interconnection are filled in the contact hole. The aluminum interconnection is formed not to directly contact the copper interconnection through the contact hole.

Abstract: A method of forming a metal interconnection structure is provided. The method includes forming an insulating layer on a semiconductor substrate including a first metal interconnection. The insulating layer is patterned to form an opening that exposes the first metal interconnection. A first diffusion barrier layer is formed on the exposed first metal interconnection. The first diffusion barrier layer comprises at least one of aluminum(Al), zirconium(Zr), silicon(Si), molybdenum(Mo), cobalt(Co), tungsten(W), ruthenium(Ru) and nickel(Ni). A second metal interconnection is formed on the first diffusion barrier layer. Metal atoms from the first metal interconnection are prevented from diffusing into the second metal interconnection by the first diffusion barrier layer. A metal interconnection structure having the first diffusion barrier layer is also provided.

Abstract: A semiconductor memory device and a method of fabricating the same are disclosed. The semiconductor memory device may include a conductive layer doped with impurities, a non-conductive layer on the conductive layer and undoped with impurities, an interlayer insulating film on the non-conductive layer and having a contact hole for exposing an upper surface of the non-conductive layer, an ohmic tungsten film on the contact hole, a lower portion of the ohmic tungsten film permeating the non-conductive layer to come in contact with the conductive layer, a tungsten nitride film on the contact hole on the ohmic tungsten film, and a tungsten film on the tungsten nitride film to fill the contact hole.

Abstract: A wafer flat zone aligner prevents wafers from binding to the walls of a wafer cassette, that define the slots in which the wafers are seated, by restricting axial movement of the wafers while the wafers are being rotated by a wafer rotating roller of the aligner. To this end, the wafer rotating roller includes a shaft portion, and a plurality of spaced apart annular members protruding radially from the shaft portion. Each wafer seated in the cassette is inserted between adjacent ones of the annular members into contact with the shaft portion of the roller. When the roller is rotated, the shaft portion rotates the wafers while the wafers are constrained from moving in the axial direction of the roller by the annular members. The wafer aligner also includes a guide roller that is moved into contact with the wafers and causes the wafers to stop rotating when flat zones of the wafer arrive at the guide roller.

Abstract: A wafer flat zone aligner prevents wafers from binding to the walls of a wafer cassette, that define the slots in which the wafers are seated, by restricting axial movement of the wafers while the wafers are being rotated by a wafer rotating roller of the aligner. To this end, the wafer rotating roller includes a shaft portion, and a plurality of spaced apart annular members protruding radially from the shaft portion. Each wafer seated in the cassette is inserted between adjacent ones of the annular members into contact with the shaft portion of the roller. When the roller is rotated, the shaft portion rotates the wafers while the wafers are constrained from moving in the axial direction of the roller by the annular members. The wafer aligner also includes a guide roller that is moved into contact with the wafers and causes the wafers to stop rotating when flat zones of the wafer arrive at the guide roller.